公开(公告)号：US20210143050A1

公开(公告)日：2021-05-13

申请号：US16676663

申请日：2019-11-07

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Ye LU ,  Haitao CHENG

IPC: H01L21/764 ,  H01L29/06 ,  H01L49/02

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device including an air gap underneath passive devices. The semiconductor device generally includes a substrate layer, a passive device layer, and a dielectric layer disposed between the substrate layer and the passive device layer, wherein the dielectric layer includes an air gap disposed beneath at least one passive device in the passive device layer.

公开(公告)号：US20200043863A1

公开(公告)日：2020-02-06

申请号：US16051525

申请日：2018-08-01

Applicant: QUALCOMM Incorporated

Inventor： Haitao CHENG ,  Ye LU ,  Chao SONG

IPC: H01L23/552 ,  H01L23/66

Abstract: Aspects generally relate to tuning a guard ring in an integrated circuit. A guard ring with a gap surrounds a circuit. The level of isolation provided by the guard ring at a particular frequency can be adjusted by coupling a tuning circuit cross the gap of the guard ring. If the circuit in the guard ring is an inductive circuit the level of inductance at a particular frequency can be adjusted by selecting the appropriate tuning circuit across the gap of the guard ring.

公开(公告)号：US20180366822A1

公开(公告)日：2018-12-20

申请号：US15687065

申请日：2017-08-25

Applicant: QUALCOMM Incorporated

Inventor： Haitao CHENG ,  Zhang JIN

IPC: H01Q1/52 ,  H01Q1/48 ,  H01Q1/22

CPC classification number: H01Q1/526 ,  H01Q1/2283 ,  H01Q1/48

Abstract: A capacitor radio frequency (RF) shielding structure may include a ground plane partially surrounding a coupling capacitor in an RF signal path. The ground plane may include a first ground plane portion extending between a positive terminal of the RF signal path and a negative terminal of the RF signal path. The ground plane may include a second ground plane portion extending between the positive terminal and the negative terminal of the RF signal path. The second ground plane portion may be opposed the first ground plane portion. The capacitor RF shielding structure may also include a patterned shielding layer electrically contacting the first ground plane portion and/or the second ground plane portion. The patterned shielding layer may electrically disconnecting a return current path over the patterned shielding layer to confine a return current to flowing over the first ground plane portion or the second ground plane portion.

公开(公告)号：US20200066829A1

公开(公告)日：2020-02-27

申请号：US16106160

申请日：2018-08-21

Applicant: Qualcomm Incorporated

Inventor： Haitao CHENG ,  Chao Song ,  Ye Lu

IPC: H01L49/02 ,  H01F17/00 ,  H01L23/522 ,  H01L27/08

Abstract: Aspects generally relate to adjusting, or lowering, the Q of an inductor. In one embodiment, an integrated circuit includes an inductor and a conductive closed ring inside a periphery of the inductor. In another embodiment, there can be a plurality of closed rings inside the periphery of the inductor. The conductive closed rings are magnetically coupled to the inductor to adjust the Q.

公开(公告)号：US20200007105A1

公开(公告)日：2020-01-02

申请号：US16023186

申请日：2018-06-29

Applicant: QUALCOMM Incorporated

Inventor： Chao SONG ,  Haitao CHENG ,  Ye LU ,  Dongjiang QIAO

IPC: H03H7/30 ,  H03H1/02 ,  H03H3/00 ,  H03H7/06 ,  H01L49/02 ,  H01L23/66 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: An integrated circuit (IC) device includes a first resistive strip having an input terminal and an output terminal. The IC device further includes a second resistive strip having a terminal coupled to a voltage. The second resistive strip may be coplanar with the first resistive strip. The IC device further includes a capacitor formed by the first resistive strip and the second resistive strip.

公开(公告)号：US20200075582A1

公开(公告)日：2020-03-05

申请号：US16115206

申请日：2018-08-28

Applicant: QUALCOMM Incorporated

Inventor： Ye LU ,  Chao SONG ,  Haitao CHENG

IPC: H01L27/06 ,  H01L27/02 ,  H01L23/522 ,  H01L49/02

Abstract: A resistor-capacitor (RC) delay circuit includes a first capacitor at a first level, a resistor at a second level and a second capacitor at a third level. The second capacitor is electrically connected in parallel with the first capacitor. The second capacitor has a footprint within a footprint of the first capacitor. The resistor is coupled in shunt with the first capacitor and the second capacitor.

公开(公告)号：US20190326872A1

公开(公告)日：2019-10-24

申请号：US15959824

申请日：2018-04-23

Applicant: QUALCOMM Incorporated

Inventor： Haitao CHENG ,  Zhang JIN

IPC: H03H7/42 ,  H01F27/42 ,  H01F27/29

Abstract: Certain aspects of the present disclosure are generally directed to a structure for a balanced-unbalanced (balun) transformer. For example, certain aspects of the present disclosure provide a transformer that generally includes a first winding having a first terminal coupled to an input node and a second terminal coupled to a reference potential node. The transformer may also include a first impedance coupled between a center tap of the first winding and the reference potential node, and a second winding magnetically coupled to the first winding and having a first terminal coupled to a first differential node of a differential output pair, a second terminal coupled to a second differential node of the differential output pair, and a center tap coupled to the reference potential node.

公开(公告)号：US20190189608A1

公开(公告)日：2019-06-20

申请号：US16004920

申请日：2018-06-11

Applicant: QUALCOMM Incorporated

Inventor： Haitao CHENG ,  Zhang JIN

IPC: H01L27/01 ,  H01L21/70 ,  H01L49/02 ,  H01L29/94 ,  H01L23/66

CPC classification number: H01L27/013 ,  H01L21/705 ,  H01L23/5222 ,  H01L23/5227 ,  H01L23/66 ,  H01L28/10 ,  H01L28/40 ,  H01L28/86 ,  H01L28/90 ,  H01L29/94

Abstract: An integrated circuit (IC) includes a capacitor array in at least one first back-end-of-line (BEOL) interconnect level. The capacitor array includes a pair of capacitor manifolds coupled to parallel capacitor routing traces and capacitors coupled between each pair of parallel capacitor routing traces. The IC also includes an inductor trace having at least one turn in at least one second BEOL interconnect level. The inductor trace defines a perimeter to overlap at least a portion of the capacitor array.

公开(公告)号：US20200083158A1

公开(公告)日：2020-03-12

申请号：US16126406

申请日：2018-09-10

Applicant: QUALCOMM Incorporated

Inventor： Chao SONG ,  Ye LU ,  Haitao CHENG

IPC: H01L23/522 ,  H01L27/01

Abstract: Certain aspects of the present disclosure provide an integrated circuit (IC) that includes at least one of a via-based vertical capacitor structure or a via-based vertical resistor structure. The IC includes a substrate oriented in a horizontal plane, electrically conductive layers disposed above the substrate, and electrically insulative layers disposed above the substrate and interposed between the plurality of electrically conductive layers. At least one of the vertical capacitor structure or the vertical resistor structure is disposed in the electrically conductive layers and the electrically insulative layers.

公开(公告)号：US20190386092A1

公开(公告)日：2019-12-19

申请号：US16009976

申请日：2018-06-15

Applicant: QUALCOMM Incorporated

Inventor： Haitao CHENG ,  Ye LU ,  Chao SONG

IPC: H01L49/02

Abstract: A capacitor has reduced misalignment in the interconnect layers and lower capacitance variance. The capacitor includes a first endcap having a first section and a second section orthogonal to the first section. The capacitor includes a first set of conductive fingers orthogonally coupled to the first section. The capacitor includes a third set of conductive fingers orthogonally coupled to the second section of the endcap and a second endcap parallel to the first section of the endcap. The capacitor includes a second set of conductive fingers orthogonally coupled to a second endcap and interdigitated with the first set of conductive fingers at a first interconnect layer. The capacitor includes a third endcap parallel to the second section of the first endcap and a fourth set of conductive fingers orthogonally coupled to the third endcap and interdigitated with the third set of conductive fingers at the first interconnect layer.