公开(公告)号：US20230300568A1

公开(公告)日：2023-09-21

申请号：US17698754

申请日：2022-03-18

Applicant: QUALCOMM Incorporated

Inventor： Liang ZHAO ,  Le Nguyen LUONG ,  Rayman Wai PON ,  Cheng-Han WANG ,  Bala RAMASAMY ,  Santosh Kumar GUPTA ,  Michael KOHLMANN

IPC: H04W4/029 ,  G08G1/005

CPC classification number: H04W4/029 ,  G08G1/005

Abstract: Disclosed are systems and techniques for wireless communications. For example, a first user equipment (UE) can receive positioning data corresponding to a second UE. In some cases, the first UE can determine a relative position between the first UE and the second UE. In some aspects, the first UE can determine a first location estimate of the first UE based on the positioning data corresponding to the second UE and the relative position between the first UE and the second UE.

公开(公告)号：US20160336910A1

公开(公告)日：2016-11-17

申请号：US14711194

申请日：2015-05-13

Applicant: QUALCOMM Incorporated

Inventor： Seyed Hossein MIRI LAVASANI ,  Cheng-Han WANG ,  Abbas KOMIJANI ,  Mohammad Bagher VAHID FAR

IPC: H03F3/19 ,  H03F1/02

CPC classification number: H03F3/19 ,  H03F1/0205 ,  H03F3/45179 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2203/45306 ,  H04B1/1036 ,  H04B2001/1045

Abstract: Certain aspects of the present disclosure provide methods and apparatus for processing an input signal. One example apparatus is a circuit that generally includes an amplifier, comprising a first transistor and a second transistor connected in cascode with the first transistor; a buffer coupled to an output of the amplifier and configured to provide feedback to the amplifier; and a current source coupled to the second transistor and incorporated into a loop of the feedback to the amplifier.

Abstract translation: 本公开的某些方面提供了用于处理输入信号的方法和装置。 一个示例性装置是通常包括放大器的电路，包括与第一晶体管共栅共享的第一晶体管和第二晶体管; 耦合到所述放大器的输出并被配置为向所述放大器提供反馈的缓冲器; 以及电流源，耦合到第二晶体管并且并入到放大器的反馈回路中。

公开(公告)号：US20250096842A1

公开(公告)日：2025-03-20

申请号：US18470195

申请日：2023-09-19

Applicant: QUALCOMM Incorporated

Inventor： Mu LU ,  Yi ZENG ,  Cheng-Han WANG ,  Ming-Tuo CHIN ,  Chan Hong PARK ,  Emanuele LOPELLI

IPC: H04B1/7183 ,  H04B1/717

Abstract: An apparatus, including: a clock source configured to generate a local oscillator (LO) clock signal; a radio frequency digital-to-analog converter (RF DAC) configured to generate a radio frequency (RF) signal based on a data signal and the LO clock signal; and an idle data detector configured to: detect a stream of idle data in the data signal; and disable providing the LO clock signal to at least a portion of the RF DAC in response to detecting the stream of idle data.

公开(公告)号：US20230300775A1

公开(公告)日：2023-09-21

申请号：US17699918

申请日：2022-03-21

Applicant: QUALCOMM Incorporated

Inventor： Le Nguyen LUONG ,  Liang ZHAO ,  Cheng-Han WANG ,  Santosh Kumar GUPTA ,  Shishir GUPTA ,  Michael KOHLMANN ,  Xiaoxin ZHANG

IPC: H04W64/00

CPC classification number: H04W64/00

Abstract: Differing operations of a wireless communication device benefit from different antenna configurations, such as for positioning, where closely spaced antennas are desirable, and data communication, where antenna diversity is desirable. A device is configured to receive a request for receive a request for determining a position of a user equipment (UE), select one of a first plurality of antennas or a second plurality of antennas for determining the position of the UE, receive wireless signals using the selected first plurality of antennas or the second plurality of antennas, and determine the position of the UE based at least in part on the received wireless signals.

公开(公告)号：US20240322925A1

公开(公告)日：2024-09-26

申请号：US18189642

申请日：2023-03-24

Applicant: QUALCOMM Incorporated

Inventor： Tu-I TSAI ,  Cheng-Han WANG ,  Yi ZENG ,  Chan Hong PARK ,  Sunghwan KIM

IPC: H04J3/06 ,  H03M1/12

CPC classification number: H04J3/0638 ,  H03M1/1255

Abstract: An apparatus, including: an oscillator configured to generate a clock signal; a clock signal synthesizer configured to generate a first clock signal, a second clock signal, and a third clock signal, wherein the first, second, and third clock signals are based on the clock signal; a baseband transmitter configured to generate a transmit baseband digital signal in response to the first clock signal; an ultra-wideband (UWB) pulse digital-to-analog converter (DAC) configured to generate a UWB pulse signal based on the transmit baseband digital signal in response to the second clock signal; and a frequency upconverter configured to frequency upconvert the UWB pulse signal to generate a transmit radio frequency (RF) signal based on the third clock signal.

公开(公告)号：US20240106496A1

公开(公告)日：2024-03-28

申请号：US17934513

申请日：2022-09-22

Applicant: QUALCOMM Incorporated

Inventor： Yi ZENG ,  Cheng-Han WANG ,  Emanuele LOPELLI ,  Chan Hong PARK ,  Liang ZHAO ,  Le Nguyen LUONG ,  Koorosh AKHAVAN

IPC: H04B1/717 ,  H03F3/24

CPC classification number: H04B1/7174 ,  H03F3/245 ,  H03F2200/09 ,  H03F2200/451

Abstract: Aspects described herein include devices and methods for smart ultra wideband transmissions. In one aspect, an apparatus includes pulse generation circuitry configured to output a plurality of transmission (TX) pulse samples at a selected signal sample rate, where each pulse sample of the plurality of TX pulse samples comprises a value associated with a pulse amplitude at a corresponding sample time The apparatus includes a plurality of power amplifier (PA) cells, with each PA cell of the plurality of PA cells comprising a corresponding current source and associated gates, and where the associated gates of a PA cell are selectable to configure an on state and an off state. Logic circuitry of the apparatus is configured to set the on state or the off state for each PA cell.

公开(公告)号：US20240098658A1

公开(公告)日：2024-03-21

申请号：US17949935

申请日：2022-09-21

Applicant: QUALCOMM Incorporated

Inventor： Yi ZENG ,  Cheng-Han WANG ,  Chan Hong PARK

IPC: H04W56/00 ,  H04L7/033

CPC classification number: H04W56/0005 ,  H04L7/0331

Abstract: An aspect of the disclosure relates to a transmitter including a phase lock loop (PLL) configured to generate a digital-to-analog (DAC) sampling signal and a local oscillator (LO) signal; a digital-to-analog (DAC) converter configured to convert a transmit digital signal into a transmit analog signal based on the DAC sampling signal; and a mixer configured to frequency upconvert the transmit analog signal based on the LO signal.

公开(公告)号：US20150271005A1

公开(公告)日：2015-09-24

申请号：US14220425

申请日：2014-03-20

Applicant: QUALCOMM Incorporated

Inventor： Cheng-Han WANG ,  I-Liang LIN ,  Liang ZHAO ,  Hong Sun KIM ,  Yi ZENG

IPC: H04L27/34 ,  H04L27/36

CPC classification number: H04L27/3405 ,  H03C2200/0041 ,  H03D3/008 ,  H03D3/009 ,  H03D2200/0045 ,  H04L27/364

Abstract: A circuit for performing a residual side band calibration is described. The circuit generally includes a phase imbalance detection circuit. The phase imbalance detection circuit may include a limiter. The phase imbalance detection circuit may be independent of gain imbalance. The circuit may also include a phase imbalance correction circuit. The phase imbalance detection circuit may control coupling between an inphase path and a quadrature path.

Abstract translation: 描述用于执行残余边带校准的电路。 该电路通常包括相位不平衡检测电路。 相位不平衡检测电路可以包括限幅器。 相位不平衡检测电路可以与增益不平衡无关。 电路还可以包括相位不平衡校正电路。 相位不平衡检测电路可以控制同相路径和正交路径之间的耦合。

公开(公告)号：US20250105928A1

公开(公告)日：2025-03-27

申请号：US18471345

申请日：2023-09-21

Applicant: QUALCOMM INCORPORATED

Inventor： Cheng-Han WANG ,  Varun Amar REDDY ,  Qi ZHOU ,  Hsin-Hsu CHEN ,  Liang ZHAO ,  Koorosh AKHAVAN ,  Yi ZENG ,  Chan Hong PARK ,  Le Nguyen LUONG

IPC: H04B17/21 ,  H04B17/00

Abstract: A system for radio frequency (RF) residual sideband (RSB) calibration includes a complex (in phase/quadrature (I/Q)) signal receiver, a signal generator configured to generate a transmit (Tx) signal, a first phase shifter operably coupled to the real signal transmitter, a first signal combiner configured to combine a receive (Rx) signal with the transmit (Tx) signal to generate a first combined signal, a second phase shifter configured to provide a selected phase shift to the first combined signal, and a complex downconverter configured to generate an in phase Rx signal and a quadrature Rx signal alternatively using an in phase LO signal and a quadrature LO signal to generate one or more signals indicative of relative Tx-Rx LO phase (θ), amplitude (A), Tx LO I/Q phase mismatch (ε), Rx I/Q amplitude mismatch (α), and Rx I/Q phase mismatch (φ) at the output of the complex receiver.

公开(公告)号：US20210257726A1

公开(公告)日：2021-08-19

申请号：US17164494

申请日：2021-02-01

Applicant: QUALCOMM Incorporated

Inventor： Sean Joel LYN ,  Cheng-Han WANG ,  Hye Jin SONG ,  Hai HUANG ,  Sang-Oh LEE

IPC: H01Q1/50 ,  H01P5/10

Abstract: An area-efficient balun and a method for signal processing using such a balun. One example balun generally includes a winding and a clamping circuit. The winding is formed by a coiled trace including a first portion having a first trace width and a second portion having a second trace width, the second trace width being narrower than the first trace width. The clamping circuit has a first terminal and a second terminal, the first terminal of the clamping circuit being coupled to the first portion of the coiled trace.