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    DRAM SUB-ARRAY LEVEL AUTONOMIC REFRESH MEMORY CONTROLLER OPTIMIZATION
    1.
    发明申请
    DRAM SUB-ARRAY LEVEL AUTONOMIC REFRESH MEMORY CONTROLLER OPTIMIZATION 有权
    DRAM SUB-ARRAY LEVEL AUTOMOMIC REFRESH MEMORY CONTROLLER OPTIMIZATION

    公开(公告)号：US20150016203A1

    公开(公告)日：2015-01-15

    申请号：US14148515

    申请日：2014-01-06

    Applicant: QUALCOMM Incorporated

    Inventor： Deepti Vijayalakshmi SRIRAMAGIRI ,  Jungwon SUH ,  Xiangyu DONG

    IPC: G11C11/406

    CPC classification number: G11C11/40618 ,  G06F13/1636 ,  G11C11/40603 ,  G11C11/40611

    Abstract: A method of refreshing a dynamic random access memory (DRAM) includes detecting an open page of the DRAM at a row of a DRAM bank within an open sub-array of the DRAM bank. The method also includes delaying issuance of a refresh command to a target refresh row of the DRAM bank when the target refresh row of the DRAM bank is within the open sub-array of the DRAM bank.

    Abstract translation: 一种刷新动态随机存取存储器（DRAM）的方法包括：检测在DRAM存储体的开放子阵列内的DRAM存储体的行的DRAM的打开页面。 该方法还包括当DRAM存储体的目标刷新行位于DRAM存储体的打开子阵列内时，向DRAM存储体的目标刷新行延迟发出刷新命令。

    DYNAMIC LINK ERROR PROTECTION IN MEMORY SYSTEMS
    2.
    发明申请
    DYNAMIC LINK ERROR PROTECTION IN MEMORY SYSTEMS 审中-公开

    公开(公告)号：US20190056990A1

    公开(公告)日：2019-02-21

    申请号：US15682533

    申请日：2017-08-21

    Applicant: QUALCOMM Incorporated

    Inventor： Jungwon SUH ,  Alain ARTIERI ,  Dexter Tamio CHUN ,  Deepti Vijayalakshmi SRIRAMAGIRI

    IPC: G06F11/10 ,  G06F3/06

    CPC classification number: G06F11/1048 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/068 ,  G06F11/10

    Abstract: Errors can be introduced when data is transferred over a link between two entities such as between a host and a memory. Link error protection schemes can be implemented to detect and correct errors that occur on the link to enhance transmission reliability. However, these benefits are not without costs since such protection schemes increase both latency and power consumption. In one or more aspects, it is proposed to dynamically adjust the level of link error protection applied to match any change in the operating environment. For example, likelihood of link errors strongly correlates with the link speed. If the link speed is increased, a greater level of link error protection can be applied to counteract the increase in the link errors. If the link speed is decreased, the level of protection can be decreased so that latency and power consumption penalties can be minimized.

    DYNAMIC LINK ERROR PROTECTION IN MEMORY SYSTEMS
    4.
    发明申请
    DYNAMIC LINK ERROR PROTECTION IN MEMORY SYSTEMS 审中-公开

    公开(公告)号：US20190324850A1

    公开(公告)日：2019-10-24

    申请号：US16503368

    申请日：2019-07-03

    Applicant: QUALCOMM Incorporated

    Inventor： Jungwon SUH ,  Alain ARTIERI ,  Dexter Tamio CHUN ,  Deepti Vijayalakshmi SRIRAMAGIRI

    IPC: G06F11/10 ,  G06F3/06

    Abstract: Errors can be introduced when data is transferred over a link between two entities such as between a host and a memory. Link error protection schemes can be implemented to detect and correct errors that occur on the link to enhance transmission reliability. However, these benefits are not without costs since such protection schemes increase both latency and power consumption. In one or more aspects, it is proposed to dynamically adjust the level of link error protection applied to match any change in the operating environment. For example, likelihood of link errors strongly correlates with the link speed. If the link speed is increased, a greater level of link error protection can be applied to counteract the increase in the link errors. If the link speed is decreased, the level of protection can be decreased so that latency and power consumption penalties can be minimized.

    OPTIMIZED ERROR-CORRECTING CODE (ECC) FOR DATA PROTECTION
    6.
    发明申请
    OPTIMIZED ERROR-CORRECTING CODE (ECC) FOR DATA PROTECTION 审中-公开

    公开(公告)号：US20180314586A1

    公开(公告)日：2018-11-01

    申请号：US15942372

    申请日：2018-03-30

    Applicant: QUALCOMM Incorporated

    Inventor： Alain ARTIERI ,  Deepti Vijayalakshmi SRIRAMAGIRI ,  Dexter Tamio CHUN ,  Jungwon SUH

    IPC: G06F11/10 ,  G06F3/06

    CPC classification number: H04L1/0041 ,  H03M13/19 ,  H04L1/0045 ,  H04L1/0057

    Abstract: Disclosed are techniques for generating a parity check matrix representing an error correcting code (ECC) for protecting a plurality of bits of a message. In an aspect, a method includes initializing a matrix M to store selected three-bit codes, selecting a first three-bit code from a set L of three-bit combinations of a number of bits n of the ECC that minimizes a sum of squared row weights of each row of the matrix M, comparing the first three-bit code with each of a plurality of error syndromes, and calculating, based on no comparison of the first three-bit code with each of the plurality of error syndromes, new error syndromes and storing the new error syndromes, wherein the new error syndromes are calculated by comparing the first three-bit code with each three-bit code in the matrix M, and storing the first three-bit code in the matrix M.

    DYNAMIC CONTROL OF SIGNALING POWER BASED ON AN ERROR RATE
    8.
    发明申请
    DYNAMIC CONTROL OF SIGNALING POWER BASED ON AN ERROR RATE 有权
    基于错误率的信号功率动态控制

    公开(公告)号：US20150332735A1

    公开(公告)日：2015-11-19

    申请号：US14280313

    申请日：2014-05-16

    Applicant: QUALCOMM Incorporated

    Inventor： Dexter Tamio CHUN ,  Vaishnav SRINIVAS ,  David Ian WEST ,  Deepti Vijayalakshmi SRIRAMAGIRI ,  Jungwon SUH ,  Jason THURSTON

    IPC: G11C5/14 ,  G06F11/07

    CPC classification number: G11C5/147 ,  G01R31/31709 ,  G01R31/3171 ,  G06F11/076 ,  G06F11/1004

    Abstract: Writing to and reading from dynamic random access memory (DRAM) by a system on chip (SoC) over a multiphase multilane memory bus has power consumption optimized based on bit error rate (BER) and one or more thresholds. The bit error rate (BER) may be measured and used to control parameters to achieve optimal balance between power consumption and accuracy. The bit error rate (BER) measurement, purposely adding jitter, and checking against the thresholds is performed during normal mission-mode operation with live traffic. Error detection may cover every memory data transaction that has a block of binary data.

    Abstract translation: 通过多相多路存储器总线通过片上系统（SoC）写入和读取动态随机存取存储器（DRAM）的功耗基于误码率（BER）和一个或多个阈值进行优化。 可以测量误码率（BER）并用于控制参数以实现功耗和精度之间的最佳平衡。 在正常任务模式操作与实时流量期间，执行误码率（BER）测量，有意添加抖动和检查阈值。 错误检测可以涵盖具有二进制数据块的每个存储器数据事务。

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