公开(公告)号：US20220129200A1

公开(公告)日：2022-04-28

申请号：US17445220

申请日：2021-08-17

Applicant: QUALCOMM Incorporated

Inventor： Victor VAN DER VEEN ,  Mosaddiq SAIFUDDIN ,  Pankaj DESHMUKH ,  Behnam DASHTIPOUR ,  David HARTLEY

IPC: G06F3/06

Abstract: A DRAM memory controller is provided that identifies a marker command directed to a given row in a DRAM. If a threshold probability is satisfied in response to an identification of the marker command, the DRAM memory controller commands the DRAM to refresh a neighboring row in the DRAM. The neighboring row may be a neighboring of the given row or of a recently-closed row.

公开(公告)号：US20170148504A1

公开(公告)日：2017-05-25

申请号：US15340266

申请日：2016-11-01

Applicant: QUALCOMM Incorporated

Inventor： Mosaddiq SAIFUDDIN ,  SankaraRao KUNAPAREDDY ,  Keunsoo ROH ,  Chun Xiang HE ,  Pratik PATEL ,  Nicholas AMBUR ,  Jeremy HAUGEN

IPC: G11C11/406 ,  G11C7/10 ,  G11C11/408

CPC classification number: G11C11/40615 ,  G06F1/3225 ,  G06F1/3275 ,  G06F13/1636 ,  G11C7/1072 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/40622 ,  G11C11/4087

Abstract: In an embodiment, a dynamic random-access memory (DRAM) system configures an inactive portion of a DRAM die to operate in accordance with a self-refresh mode that is characterized by refreshes of the DRAM die being controlled by a local DRAM die controller integrated into the DRAM die. The DRAM system also configures an active portion of the DRAM die to operate in accordance with a controller-managed refresh mode while the inactive portion of the DRAM die operates in the self-refresh mode, the controller-managed refresh mode characterized by refreshes of the DRAM die being controlled by a controller that is external to the DRAM die.

公开(公告)号：US20160307645A1

公开(公告)日：2016-10-20

申请号：US14691570

申请日：2015-04-20

Applicant: Qualcomm Incorporated

Inventor： Jung Pill KIM ,  Dexter Tamio CHUN ,  Jungwon SUH ,  Deepti Vijayalakshmi SRIRAMAGIRI ,  Yanru LI ,  Mosaddiq SAIFUDDIN ,  Xiangyu DONG

IPC: G11C29/44 ,  G06F11/07 ,  G11C29/00

CPC classification number: G11C29/4401 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/079 ,  G06F11/0793 ,  G06F11/1048 ,  G11C11/401 ,  G11C29/42 ,  G11C29/76

Abstract: A memory having a redundancy area is operated in a normal mode and an error is detected. A selecting selects between in-line repair process and off-line repair. In-line repair applies a short term error correction, which remaps a fail address to a remapped memory area of the memory. An in-system repair is applied, for a one-time programmed remapping of the fail address to a redundancy area of the memory. In-system repair utilizes idle time of the memory to maintain valid memory content.

Abstract translation: 具有冗余区域的存储器在正常模式下操作并且检测到错误。 选择选择在线修复过程和离线修复。 在线修复应用短期错误纠正，其将失败地址重映射到存储器的重映射存储区域。 应用系统内修复，将故障地址的一次性重新映射重新映射到存储器的冗余区域。 系统内修复利用存储器的空闲时间来维护有效的存储器内容。

公开(公告)号：US20250094264A1

公开(公告)日：2025-03-20

申请号：US18470333

申请日：2023-09-19

Applicant: QUALCOMM Incorporated

Inventor： Mohsin RIAZ ,  Tamer KAFAFI ,  Xavier Loic LELOUP ,  Mosaddiq SAIFUDDIN

IPC: G06F11/07 ,  G06F9/30

Abstract: Various embodiments include methods and devices for implementing a scan dump of memory subsystem cores. Embodiments may include enabling a scan dump path of the memory subsystem during a computing device crash reset flow, the scan dump path comprising at least one memory controller having at least one scan dump logic module, a scan dump network on chip (NoC) module, and at least one scan dump data bus connecting the at least one scan dump logic module and the scan dump NoC, and initializing a scan mode for a memory path of the memory subsystem and for a low power memory path of the memory subsystem.

公开(公告)号：US20150261632A1

公开(公告)日：2015-09-17

申请号：US14458009

申请日：2014-08-12

Applicant: QUALCOMM Incorporated

Inventor： Jung Pill KIM ,  Dexter Tamio CHUN ,  Deepti Vijayalakshmi SRIRAMAGIRI ,  Mosaddiq SAIFUDDIN ,  Xiangyu DONG ,  Sungryul KIM ,  Yanru LI ,  Jungwon SUH

IPC: G06F11/20 ,  G11C29/52

CPC classification number: G06F11/2053 ,  G06F11/073 ,  G06F11/0775 ,  G06F11/0793 ,  G06F11/08 ,  G06F11/1048 ,  G06F11/3037 ,  G11C29/4401 ,  G11C29/52 ,  G11C2029/0409

Abstract: Methods and systems for an in-system repair process that repairs or attempts to repair random bit failures in a memory device are provided. In some examples, an in-system repair process may select alternative steps depending on whether the failure is correctable or uncorrectable. In these examples, the process uses communications between a system on chip and the memory to fix the failures during normal operation.

Abstract translation: 提供了修复或尝试修复存​​储器件中的随机位故障的系统内修复过程的方法和系统。 在一些示例中，系统内修复过程可以根据故障是可校正还是不可校正来选择替代步骤。 在这些示例中，该过程使用片上系统与存储器之间的通信来在正常操作期间修复故障。