公开(公告)号：US20180081806A1

公开(公告)日：2018-03-22

申请号：US15273182

申请日：2016-09-22

Applicant: QUALCOMM Incorporated

Inventor： Vignyan Reddy KOTHINTI NARESH ,  Anil KRISHNA ,  Gregory Michael WRIGHT

IPC: G06F12/0815 ,  G06F9/30

CPC classification number: G06F12/0862 ,  G06F9/3834 ,  G06F9/3842 ,  G06F2212/1021 ,  G06F2212/1032 ,  G06F2212/452 ,  G06F2212/6022 ,  G06F2212/6028

Abstract: Disclosed are methods and apparatuses for preventing memory violations. In an aspect, a fetch unit accesses, from a branch predictor of a processor, a disambiguation indicator associated with a block of instructions of a program to be executed by the processor, and fetches, from an instruction cache, the block of instructions. The processor executes load instructions and/or store instructions in the block of instructions based on the disambiguation indicator indicating whether or not the load instructions and/or the store instructions in the block of instructions can bypass other instructions of the program or be bypassed by other instructions of the program.

公开(公告)号：US20190013062A1

公开(公告)日：2019-01-10

申请号：US15644737

申请日：2017-07-07

Applicant: QUALCOMM Incorporated

Inventor： Francois Ibrahim ATALLAH ,  Gregory Michael WRIGHT ,  Shivam PRIYADARSHI ,  Garrett Michael DRAPALA ,  Harold Wade CAIN, III ,  Erik HEDBERG

IPC: G11C11/406 ,  G06F12/128 ,  G06F12/122 ,  G06F12/0871

Abstract: Systems and methods for selective refresh of a cache, such as a last-level cache implemented as an embedded DRAM (eDRAM). A refresh bit and a reuse bit are associated with each way of at least one set of the cache. A least recently used (LRU) stack tracks positions of the ways, with positions towards a most recently used position of a threshold comprising more recently used positions and positions towards a least recently used position of the threshold comprise less recently used positions. A line in a way is selectively refreshed if the position of the way is one of the more recently used positions and if the refresh bit associated with the way is set, or the position of the way is one of the less recently used positions and if the refresh bit and the reuse bit associated with the way are both set.

公开(公告)号：US20180089085A1

公开(公告)日：2018-03-29

申请号：US15274615

申请日：2016-09-23

Applicant: QUALCOMM Incorporated

Inventor： Vignyan Reddy KOTHINTI NARESH ,  Gregory Michael WRIGHT

IPC: G06F12/0862

CPC classification number: G06F12/0862 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0897 ,  G06F2212/1016 ,  G06F2212/602 ,  G06F2212/6024 ,  G06F2212/6026 ,  G06F2212/655

Abstract: A proposed prefetcher may operate at a cache level where accesses are conducted using physical addresses. The proposed prefetcher may include one or more prefetch engines. Similar to conventional prefetchers, a prefetch engines of the proposed prefetcher may train on access patterns of a memory page to predict future accesses and perform prefetches based on the training. But unlike the conventional prefetchers, the trained prefetch engine may be reused for prefetching even when a request for a new page is received without requiring the prefetch engine to be newly trained on the new page. This can lower access latencies and lower cumulative training time.

公开(公告)号：US20160232006A1

公开(公告)日：2016-08-11

申请号：US14617910

申请日：2015-02-09

Applicant: QUALCOMM Incorporated

Inventor： Gregory Michael WRIGHT

IPC: G06F9/30

CPC classification number: G06F9/3859 ,  G06F9/30101 ,  G06F9/30163 ,  G06F9/30185 ,  G06F9/3826 ,  G06F9/3836 ,  G06F9/3844 ,  G06F9/3853

Abstract: An apparatus for fan out of a result of a first instruction can include first through fourth sets of memory cells and circuitry. The first set can be configured to store the result of the first instruction. The second set can be configured to store an operation code of a second instruction. The third set can be configured to store information of the second instruction. The fourth set can be configured to store an operand for the second instruction. The circuitry can be configured to connect the fourth set to an execution unit and to cause, in response to a presence of the information in the third set, the execution unit to be configured to receive a content of the first set as the operand for the second instruction. A format of the second instruction can include a sets of bits designated for the operation code and for the information.

Abstract translation: 由第一指令的结果引起的风扇装置可以包括第一至第四组存储器单元和电路。 第一组可以配置为存储第一条指令的结果。 第二组可以被配置为存储第二指令的操作码。 第三组可以配置为存储第二条指令的信息。 第四组可以配置为存储第二条指令的操作数。 电路可以被配置为将第四集合连接到执行单元，并且响应于第三组中的信息的存在而导致执行单元被配置为接收第一集合的内容作为用于 第二个指令。 第二指令的格式可以包括为操作码和信息指定的一组比特。

公开(公告)号：US20160019039A1

公开(公告)日：2016-01-21

申请号：US14867122

申请日：2015-09-28

Applicant: QUALCOMM Incorporated

Inventor： Soorgoli Ashok HALAMBI ,  Gregory Michael WRIGHT ,  Christopher VICK

IPC: G06F9/45

CPC classification number: G06F8/447 ,  G06F8/443 ,  G06F9/45516

Abstract: The various aspects provide a dynamic compilation framework that includes a machine-independent optimization module operating on a computing device and methods for optimizing code with the machine-independent optimization module using a single, combined-forwards-backwards pass of the code. In the various aspects, the machine-independent optimization module may generate a graph of nodes from the IR, optimize nodes in the graph using forwards and backwards optimizations, and propagating the forwards and backwards optimizations to nodes in a bounded subgraph recognized or defined based on the position of the node currently being optimized. In the various aspects, the machine-independent optimization module may optimize the graph by performing forwards and/or backwards optimizations during a single pass through the graph, thereby achieving an effective degree of optimization and shorter overall compile times. Thus, the various aspects may provide a global optimization framework for dynamic compilers that is faster and more efficient than existing solutions.

公开(公告)号：US20190087241A1

公开(公告)日：2019-03-21

申请号：US15712121

申请日：2017-09-21

Applicant: QUALCOMM Incorporated

Inventor： Vignyan Reddy KOTHINTI NARESH ,  Gregory Michael WRIGHT

IPC: G06F9/52

Abstract: Systems and methods are directed to efficient management of processor resources, particularly General Purpose Registers (GPRs), for example to minimize pipeline flushes prevent deadlocks by counting GPRs instead of allocating them to specific blocks of code. Blocks of code are allowed to execute if the Free GPRs count is adequate. The method contemplates counting the number of Register Writers in blocks of code which will write to GPRs which are in process of executing, and counting the GPRs which are available instead of merely allocating them to dedicated use by a block of code, or an instruction in a block of code. Because blocks do not run if there is not enough GPRs available for the block, deadlocks and pipeline flushes due to lack of resources can be minimized.

公开(公告)号：US20180232233A1

公开(公告)日：2018-08-16

申请号：US15431763

申请日：2017-02-13

Applicant: QUALCOMM Incorporated

Inventor： Gregory Michael WRIGHT

IPC: G06F9/38 ,  G06F12/0813 ,  G06F12/0864 ,  G06F12/1009 ,  G06F12/0842 ,  G06F12/02 ,  G06F12/06

Abstract: The disclosure relates to processing in-flight blocks in a processor pipeline according to an expected execution mode to reduce synchronization delays that could otherwise arise due to transitions among processor modes with varying privilege levels (e.g., user mode, supervisor mode, hypervisor mode, etc.). More particularly, a program counter associated with an instruction block to be fetched may be translated to one or more execute permissions associated with the instruction block and the instruction block may be associated with a speculative execution mode based at least in part on the one or more execute permissions. Accordingly, the instruction block may be processed relative to the speculative execution mode while in-flight within the processor pipeline.

公开(公告)号：US20170060750A1

公开(公告)日：2017-03-02

申请号：US14843958

申请日：2015-09-02

Applicant: QUALCOMM Incorporated

Inventor： Anil KRISHNA ,  Gregory Michael WRIGHT ,  Derek Robert HOWER

IPC: G06F12/08

CPC classification number: G06F12/0895 ,  G06F2212/1021

Abstract: Method and apparatus for cache way prediction using a plurality of partial tags are provided. In a cache-block address comprising a plurality of sets and a plurality of ways or lines, one of the sets is selected for indexing, and a plurality of distinct partial tags are identified for the selected set. A determination is made as to whether a partial tag for a new line collides with any of the partial tags for current resident lines in the selected set. If the partial tag for the new line does not collide with any of the partial tags for the current resident lines, then there is no aliasing. If the partial tag for the new line collides with any of the partial tags for the current resident lines, then aliasing may be avoided by reading the full tag array and updating the partial tags.

Abstract translation: 提供了使用多个部分标签的高速缓存方式预测的方法和装置。 在包括多个集合和多个方式或行的高速缓存块地址中，选择该集合中的一个用于索引，并为所选择的集合识别多个不同的部分标签。 确定新行的部分标签是否与所选集合中当前居民行的任何部分标签相冲突。 如果新行的部分标签不与当前居民行的任何部分标签相冲突，则不存在别名。 如果新行的部分标签与当前驻留行的任何部分标签相冲突，则可以通过读取完整标记数组并更新部分标签来避免混叠。

公开(公告)号：US20160259645A1

公开(公告)日：2016-09-08

申请号：US14639085

申请日：2015-03-04

Applicant: QUALCOMM Incorporated

Inventor： Gregory Michael WRIGHT

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/384 ,  G06F9/30145 ,  G06F9/3836

Abstract: An apparatus for mapping an architectural register to a physical register can include a memory and control circuitry. The memory can be configured to store an intra-core register rename map and an inter-core register rename map. The intra-core register rename map can be configured to map the architectural register to the physical register of a core of a multi-core processor. The inter-core register rename map can be configured to relate the architectural register to an identification of the first core in response to determining that the physical register is a location of a most recent write to the architectural register that has been executed by the first core, is executing on the first core, or is expected to execute on the first core, the most recent write according to program order. The control circuitry can be configured to maintain the intra-core register rename map and the inter-core register rename map.

Abstract translation: 用于将架构寄存器映射到物理寄存器的装置可以包括存储器和控制电路。 存储器可被配置为存储核心内寄存器重命名映射和核心间寄存器重命名映射。 内核寄存器重命名映射可以配置为将体系结构寄存器映射到多核处理器核心的物理寄存器。 响应于确定物理寄存器是对由第一核心执行的架构寄存器的最新写入的位置，可以将核心间寄存器重命名映射配置为将体系结构寄存器与第一核心的标识相关联 ，正在第一个核心上执行，或者预计在第一个核心上执行最新的根据程序命令的写入。 控制电路可以配置为保持核心内寄存器重命名映射和核心间寄存器重命名映射。