公开(公告)号：US09998099B2

公开(公告)日：2018-06-12

申请号：US14384374

申请日：2014-05-23

Applicant: QUALCOMM Incorporated

Inventor： Wenjun Su ,  Chulkyu Lee ,  Le Zhang ,  Guangming Yin

IPC: G05F1/00 ,  H02M3/07 ,  H03K5/159 ,  H03K3/011 ,  H03K17/14 ,  H03K19/003 ,  G05F3/26

CPC classification number: H03K3/011 ,  G05F1/00 ,  G05F3/205 ,  G05F3/242 ,  G05F3/262 ,  H02M3/07 ,  H03K5/159 ,  H03K17/145 ,  H03K19/00384 ,  H03K2217/0018

Abstract: A feed-forward bias circuit biases body bias terminals of transistors of another circuit to compensate for PVT variations in the other circuit. In some aspects, the feed-forward bias circuit compensates for transistor process corners in a circuit by enabling the generation of different bias signals under different corner conditions. In some implementations, the feed-forward bias circuit is used to bias a delay circuit so that the delay circuit exhibits relatively constant delay characteristics over different PVT conditions.

公开(公告)号：US20170077907A1

公开(公告)日：2017-03-16

申请号：US14384374

申请日：2014-05-23

Applicant: QUALCOMM INCORPORATED

Inventor： Wenjun Su ,  Chulkyu Lee ,  Le Zhang ,  Guangming Yin

IPC: H03K3/011 ,  G05F3/26 ,  H03K5/159

CPC classification number: H03K3/011 ,  G05F1/00 ,  G05F3/205 ,  G05F3/242 ,  G05F3/262 ,  H02M3/07 ,  H03K5/159 ,  H03K17/145 ,  H03K19/00384 ,  H03K2217/0018

Abstract: A feed-forward bias circuit biases body bias terminals of transistors of another circuit to compensate for PVT variations in the other circuit. In some aspects, the feed-forward bias circuit compensates for transistor process corners in a circuit by enabling the generation of different bias signals under different corner conditions. In some implementations, the feed-forward bias circuit is used to bias a delay circuit so that the delay circuit exhibits relatively constant delay characteristics over different PVT conditions.

Abstract translation: 前馈偏置电路偏置另一电路的晶体管的体偏置端子，以补偿另一电路中的PVT变化。 在一些方面，前馈偏置电路通过在不同的拐角条件下产生不同的偏置信号来补偿电路中的晶体管工艺角。 在一些实现中，前馈偏置电路用于偏置延迟电路，使得延迟电路在不同的PVT条件下表现出相对恒定的延迟特性。

公开(公告)号：US10007320B2

公开(公告)日：2018-06-26

申请号：US15302767

申请日：2014-05-21

Applicant: QUALCOMM Incorporated

Inventor： Le Zhang ,  Wenjun Su ,  Chulkyu Lee

IPC: G06F13/00 ,  G06F1/32 ,  H03M9/00 ,  G06F1/08 ,  G06F13/40 ,  G06F13/42 ,  G11C19/28

CPC classification number: G06F1/324 ,  G06F1/08 ,  G06F13/4022 ,  G06F13/4282 ,  G11C19/28 ,  H03M9/00 ,  Y02D10/14 ,  Y02D10/151

Abstract: Serializers and deserializers for odd ratio parallel data buses are disclosed. In one embodiment, serializers and deserializers operating with an odd number of parallel data bits work with a half-rate clock to provide a serial data stream at a full clock rate. By providing a half-rate clock, power and area are conserved on the integrated circuit incorporating the serializer. Additionally, by providing a 7:1 serializer, the bus is now compatible with the MIPI C-PHY standard.

公开(公告)号：US09971392B2

公开(公告)日：2018-05-15

申请号：US15302767

申请日：2014-05-21

Applicant: QUALCOMM Incorporated

Inventor： Le Zhang ,  Wenjun Su ,  Chulkyu Lee

IPC: G06F13/00 ,  G06F1/32 ,  H03M9/00 ,  G06F1/08 ,  G06F13/40 ,  G06F13/42 ,  G11C19/28

Abstract: Serializers and deserializers for odd ratio parallel data buses are disclosed. In one embodiment, serializers and deserializers operating with an odd number of parallel data bits work with a half-rate clock to provide a serial data stream at a full clock rate. By providing a half-rate clock, power and area are conserved on the integrated circuit incorporating the serializer. Additionally, by providing a 7:1 serializer, the bus is now compatible with the MIPI C-PHY standard.

公开(公告)号：US20170060218A1

公开(公告)日：2017-03-02

申请号：US15302767

申请日：2014-05-21

Applicant: Wenjen SU ,  Le ZHANG ,  Chulkyu LEE ,  QUALCOMM Incorporated

Inventor： Le Zhang ,  Wenjun Su ,  Chulkyu Lee

IPC: G06F1/32 ,  G06F13/42 ,  G06F1/08 ,  G06F13/40 ,  H03M9/00 ,  G11C19/28

CPC classification number: G06F1/324 ,  G06F1/08 ,  G06F13/4022 ,  G06F13/4282 ,  G11C19/28 ,  H03M9/00 ,  Y02D10/14 ,  Y02D10/151

Abstract: Serializers and deserializers for odd ratio parallel data buses are disclosed. In one embodiment, serializers and deserializers operating with an odd number of parallel data bits work with a half-rate clock to provide a serial data stream at a full clock rate. By providing a half-rate clock, power and area are conserved on the integrated circuit incorporating the serializer. Additionally, by providing a 7:1 serializer, the bus is now compatible with the MIPI C-PHY standard.

Abstract translation: 公开了用于奇数比并行数据总线的串行器和解串器。 在一个实施例中，以奇数个并行数据位操作的串行器和解串行器与半速率时钟一起工作，以全时钟速率提供串行数据流。 通过提供半速率时钟，集成了串行器的集成电路的功率和面积是保守的。 此外，通过提供7：1串行器，该总线现在与MIPI C-PHY标准兼容。

公开(公告)号：US09148198B1

公开(公告)日：2015-09-29

申请号：US14284293

申请日：2014-05-21

Applicant: QUALCOMM Incorporated

Inventor： Le Zhang ,  Chulkyu Lee ,  Wenjun Su

IPC: H04L27/00 ,  H04B3/04

CPC classification number: H04B3/04 ,  H04L25/0264 ,  H04L25/03343 ,  H04L25/49

Abstract: System, methods and apparatus are described that improve signaling in a three-wire multiphase communication link. A method for data communications includes determining a transition in signaling state of three wires of a communication link between a pair of consecutive symbols transmitted on the communication link, and enhancing or attenuating energy of a signal prior to the transition in signaling state of the three wires when the transition in signaling state includes a change in signaling state of a wire on which the signal is transmitted. Each symbol may define a different signaling state of the three wires of the communication link. For each symbol transmitted, two of the three wires are differentially encoded and the third wire is in a neutral state. Different wires are differentially encoded during transmission of consecutive symbols.

Abstract translation: 描述了改进三线多相通信链路中的信令的系统，方法和装置。 一种用于数据通信的方法包括确定在通信链路上发送的一对连续符号之间的通信链路的三条线路的信令状态的转换，以及增强或衰减在三条线路的信令状态下的转换之前的信号能量 当信令状态的转换包括发送信号的线路的信令状态的变化时。 每个符号可以定义通信链路的三条线的不同的信令状态。 对于发送的每个符号，三条线中的两条被差分编码，第三条线处于中性状态。 不同的导线在连续符号的传输期间进行差分编码。