公开(公告)号：US09804991B2

公开(公告)日：2017-10-31

申请号：US14636504

申请日：2015-03-03

Applicant: QUALCOMM Incorporated

Inventor： Chad Everett Winemiller ,  Jon Raymond Boyette ,  Russell Coleman Deans

IPC: G06F13/42 ,  G06F13/40 ,  G01R31/317

CPC classification number: G06F13/4282 ,  G01R31/31705 ,  G06F13/4027

Abstract: Aspects disclosed in the detailed description include high-frequency signal observations in electronic systems. In this regard, a high-frequency signal observation circuit is provided in an electronic system to enable high-frequency signal observations. In one aspect, the high-frequency signal observation circuit comprises an observation signal selection circuit. The observation signal selection circuit is programmably controlled to select an observation signal among a plurality of electronic input signals (e.g., control signals) received from the electronic system. In another aspect, the high-frequency signal observation circuit is configured to utilize a bypass data path, which is routed around serializer/deserializer (SerDes) logic in the electronic system, to output the observation signal for observation. By programmably selecting the observation signal and outputting the observation signal via the bypass data path, it is possible to examine accurately any high-frequency signal (e.g., high-frequency clock signal) in the electronic system with minimized delay and/or degradation in the high-frequency signal.

公开(公告)号：US09509318B2

公开(公告)日：2016-11-29

申请号：US14657225

申请日：2015-03-13

Applicant: QUALCOMM Incorporated

Inventor： Chad Everett Winemiller ,  Behnam Amelifard ,  Kenneth Luis Arcudia ,  Jon Raymond Boyette ,  Chia Heng Chang ,  Russell Coleman Deans ,  Kevin Wayne Spears

IPC: H03K3/00 ,  H03L7/08 ,  G06F1/12

CPC classification number: G06F1/12 ,  G06F1/04 ,  G06F1/3237 ,  G06F1/3293 ,  Y02D10/122 ,  Y02D10/128

Abstract: Aspects disclosed in the detailed description include apparatuses, methods, and systems for glitch-free clock switching. In this regard, in one aspect, an electronic circuit is switched from a lower-frequency reference clock to a higher-frequency reference clock. An oscillation detection logic is configured to determine the stability of the higher-frequency reference clock prior to switching the electronic circuit to the higher-frequency reference clock. The oscillation detection logic derives a sampled clock signal from the higher-frequency reference clock, wherein the sampled clock signal has a slower frequency than the lower-frequency reference clock. The oscillation detection logic then compares the sampled clock signal against the lower-frequency reference clock to determine the stability of the higher-frequency reference clock. By deterministically detecting stability of a reference clock prior to switching to the reference clock, it is possible to avoid premature switching to an unstable reference clock, thus providing glitch-free clock switching in the electronic circuit.

Abstract translation: 在详细描述中公开的方面包括用于无毛刺时钟切换的装置，方法和系统。 在这方面，在一个方面，电子电路从低频参考时钟切换到较高频率参考时钟。 振荡检测逻辑被配置为在将电子电路切换到较高频率参考时钟之前确定较高频率参考时钟的稳定性。 振荡检测逻辑从较高频率参考时钟导出采样时钟信号，其中采样时钟信号的频率比低频参考时钟慢。 振荡检测逻辑然后将采样的时钟信号与较低频率参考时钟进行比较，以确定较高频率参考时钟的稳定性。 通过在切换到参考时钟之前确定性地检测参考时钟的稳定性，可以避免过早切换到不稳定的参考时钟，从而在电子电路中提供无毛刺的时钟切换。

公开(公告)号：US20170329386A1

公开(公告)日：2017-11-16

申请号：US15150586

申请日：2016-05-10

Applicant: QUALCOMM Incorporated

Inventor： Chad Everett Winemiller ,  Jon Raymond Boyette ,  Russell Coleman Deans ,  Zhi Zhu

IPC: G06F1/32 ,  G06F13/42

CPC classification number: G06F1/3278 ,  G06F1/3209 ,  G06F1/3215 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3253 ,  G06F1/3287

Abstract: Power saving systems and methods for Universal Serial Bus (USB) systems are disclosed. When a USB physical layer (PHY) enters a U3 low power state, not only are normal elements powered down, but also circuitry within the USB PHY associated with detection of a low frequency periodic signal (LFPS) wake up signal is powered down. A low speed reference clock signal is still received by the USB PHY, and a medium speed clock within the USB PHY is activated once per period of the low speed reference clock signal. The medium speed clock activates the signal detection circuitry and samples a line for the LFPS. If no LFPS is detected, the signal detection circuitry and the medium speed clock return to low power until the next period of the low speed reference clock signal. If the LFPS is detected, the USB PHY returns to a U0 active power state.

公开(公告)号：US20160269034A1

公开(公告)日：2016-09-15

申请号：US14657225

申请日：2015-03-13

Applicant: QUALCOMM Incorporated

Inventor： Chad Everett Winemiller ,  Behnam Amelifard ,  Kenneth Luis Arcudia ,  Jon Raymond Boyette ,  Chia Heng Chang ,  Russell Coleman Deans ,  Kevin Wayne Spears

IPC: H03L7/08 ,  G06F1/12

CPC classification number: G06F1/12 ,  G06F1/04 ,  G06F1/3237 ,  G06F1/3293 ,  Y02D10/122 ,  Y02D10/128

Abstract: Aspects disclosed in the detailed description include apparatuses, methods, and systems for glitch-free clock switching. In this regard, in one aspect, an electronic circuit is switched from a lower-frequency reference clock to a higher-frequency reference clock. An oscillation detection logic is configured to determine the stability of the higher-frequency reference clock prior to switching the electronic circuit to the higher-frequency reference clock. The oscillation detection logic derives a sampled clock signal from the higher-frequency reference clock, wherein the sampled clock signal has a slower frequency than the lower-frequency reference clock. The oscillation detection logic then compares the sampled clock signal against the lower-frequency reference clock to determine the stability of the higher-frequency reference clock. By deterministically detecting stability of a reference clock prior to switching to the reference clock, it is possible to avoid premature switching to an unstable reference clock, thus providing glitch-free clock switching in the electronic circuit.

Abstract translation: 在详细描述中公开的方面包括用于无毛刺时钟切换的装置，方法和系统。 在这方面，在一个方面，电子电路从低频参考时钟切换到较高频率参考时钟。 振荡检测逻辑被配置为在将电子电路切换到较高频率参考时钟之前确定较高频率参考时钟的稳定性。 振荡检测逻辑从较高频率参考时钟导出采样时钟信号，其中采样时钟信号的频率比低频参考时钟慢。 振荡检测逻辑然后将采样的时钟信号与较低频率参考时钟进行比较，以确定较高频率参考时钟的稳定性。 通过在切换到参考时钟之前确定性地检测参考时钟的稳定性，可以避免过早切换到不稳定的参考时钟，从而在电子电路中提供无毛刺的时钟切换。

公开(公告)号：US09829958B1

公开(公告)日：2017-11-28

申请号：US15150586

申请日：2016-05-10

Applicant: QUALCOMM Incorporated

Inventor： Chad Everett Winemiller ,  Jon Raymond Boyette ,  Russell Coleman Deans ,  Zhi Zhu

IPC: G06F1/32

CPC classification number: G06F1/3278 ,  G06F1/3209 ,  G06F1/3215 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3253 ,  G06F1/3287

Abstract: Power saving systems and methods for Universal Serial Bus (USB) systems are disclosed. When a USB physical layer (PHY) enters a U3 low power state, not only are normal elements powered down, but also circuitry within the USB PHY associated with detection of a low frequency periodic signal (LFPS) wake up signal is powered down. A low speed reference clock signal is still received by the USB PHY, and a medium speed clock within the USB PHY is activated once per period of the low speed reference clock signal. The medium speed clock activates the signal detection circuitry and samples a line for the LFPS. If no LFPS is detected, the signal detection circuitry and the medium speed clock return to low power until the next period of the low speed reference clock signal. If the LFPS is detected, the USB PHY returns to a U0 active power state.

公开(公告)号：US20160259755A1

公开(公告)日：2016-09-08

申请号：US14636504

申请日：2015-03-03

Applicant: QUALCOMM Incorporated

Inventor： Chad Everett Winemiller ,  Jon Raymond Boyette ,  Russell Coleman Deans

IPC: G06F13/42 ,  G06F13/40

CPC classification number: G06F13/4282 ,  G01R31/31705 ,  G06F13/4027

Abstract: Aspects disclosed in the detailed description include high-frequency signal observations in electronic systems. In this regard, a high-frequency signal observation circuit is provided in an electronic system to enable high-frequency signal observations. In one aspect, the high-frequency signal observation circuit comprises an observation signal selection circuit. The observation signal selection circuit is programmably controlled to select an observation signal among a plurality of electronic input signals (e.g., control signals) received from the electronic system. In another aspect, the high-frequency signal observation circuit is configured to utilize a bypass data path, which is routed around serializer/deserializer (SerDes) logic in the electronic system, to output the observation signal for observation. By programmably selecting the observation signal and outputting the observation signal via the bypass data path, it is possible to examine accurately any high-frequency signal (e.g., high-frequency clock signal) in the electronic system with minimized delay and/or degradation in the high-frequency signal.

Abstract translation: 在详细描述中公开的方面包括电子系统中的高频信号观测。 在这方面，在电子系统中设置高频信号观测电路，以实现高频信号观测。 一方面，高频信号观测电路包括观测信号选择电路。 可编程地控制观测信号选择电路以从从电子系统接收的多个电子输入信号（例如，控制信号）中选择观测信号。 在另一方面，高频信号观测电路被配置为利用绕在电子系统中的串行器/解串器（SerDes）逻辑路由的旁路数据路径，以输出用于观察的观测信号。 通过可编程地选择观测信号并通过旁路数据路径输出观测信号，可以精确地检查电子系统中的任何高频信号（例如，高频时钟信号），其中最小的延迟和/或劣化 高频信号。