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    Apparatuses, methods, and systems for glitch-free clock switching
    1.
    发明授权
    Apparatuses, methods, and systems for glitch-free clock switching 有权
    无干扰时钟切换的设备，方法和系统

    公开(公告)号：US09509318B2

    公开(公告)日：2016-11-29

    申请号：US14657225

    申请日：2015-03-13

    Applicant: QUALCOMM Incorporated

    Inventor： Chad Everett Winemiller ,  Behnam Amelifard ,  Kenneth Luis Arcudia ,  Jon Raymond Boyette ,  Chia Heng Chang ,  Russell Coleman Deans ,  Kevin Wayne Spears

    IPC: H03K3/00 ,  H03L7/08 ,  G06F1/12

    CPC classification number: G06F1/12 ,  G06F1/04 ,  G06F1/3237 ,  G06F1/3293 ,  Y02D10/122 ,  Y02D10/128

    Abstract: Aspects disclosed in the detailed description include apparatuses, methods, and systems for glitch-free clock switching. In this regard, in one aspect, an electronic circuit is switched from a lower-frequency reference clock to a higher-frequency reference clock. An oscillation detection logic is configured to determine the stability of the higher-frequency reference clock prior to switching the electronic circuit to the higher-frequency reference clock. The oscillation detection logic derives a sampled clock signal from the higher-frequency reference clock, wherein the sampled clock signal has a slower frequency than the lower-frequency reference clock. The oscillation detection logic then compares the sampled clock signal against the lower-frequency reference clock to determine the stability of the higher-frequency reference clock. By deterministically detecting stability of a reference clock prior to switching to the reference clock, it is possible to avoid premature switching to an unstable reference clock, thus providing glitch-free clock switching in the electronic circuit.

    Abstract translation: 在详细描述中公开的方面包括用于无毛刺时钟切换的装置，方法和系统。 在这方面，在一个方面，电子电路从低频参考时钟切换到较高频率参考时钟。 振荡检测逻辑被配置为在将电子电路切换到较高频率参考时钟之前确定较高频率参考时钟的稳定性。 振荡检测逻辑从较高频率参考时钟导出采样时钟信号，其中采样时钟信号的频率比低频参考时钟慢。 振荡检测逻辑然后将采样的时钟信号与较低频率参考时钟进行比较，以确定较高频率参考时钟的稳定性。 通过在切换到参考时钟之前确定性地检测参考时钟的稳定性，可以避免过早切换到不稳定的参考时钟，从而在电子电路中提供无毛刺的时钟切换。

    Thermometer code converter
    2.
    发明授权
    Thermometer code converter 有权
    温度计代码转换器

    公开(公告)号：US09356614B1

    公开(公告)日：2016-05-31

    申请号：US14604616

    申请日：2015-01-23

    Applicant: QUALCOMM Incorporated

    Inventor： Behnam Amelifard ,  Hadi Goudarzi ,  Chia Heng Chang

    IPC: H03M7/16 ,  H03M1/10 ,  H03M1/00 ,  G11C19/28

    CPC classification number: H03M1/1009 ,  G11C19/28 ,  H03M1/002 ,  H03M7/165 ,  H03M7/6047

    Abstract: A code converter is provided. The code converter includes a plurality of serial shift registers arranged to convert an input to a thermometer output. The code converter further includes a plurality of clock control circuits each configured to provide a clock to a corresponding one of the shift registers. A method of generating a signal in thermometer code is provided. The method includes enabling a subset of a plurality of shift registers and converting an input to a thermometer output by the plurality of shift registers. Another code converter is further provided. The code converter includes means for converting an input to a thermometer output. The means for converting includes a plurality of shift registers. The code converter further includes means for enabling a subset of the shift registers.

    Abstract translation: 提供代码转换器。 代码转换器包括多个串行移位寄存器，用于将输入转换为温度计输出。 代码转换器还包括多个时钟控制电路，每个时钟控制电路被配置为向对应的一个移位寄存器提供时钟。 提供了一种以温度计代码生成信号的方法。 该方法包括启用多个移位寄存器的子集，并将输入转换为多个移位寄存器的温度计输出。 还提供另一代码转换器。 代码转换器包括用于将输入转换为温度计输出的装置。 用于转换的装置包括多个移位寄存器。 代码转换器还包括用于启用移位寄存器的子集的装置。

    APPARATUSES, METHODS, AND SYSTEMS FOR GLITCH-FREE CLOCK SWITCHING
    4.
    发明申请
    APPARATUSES, METHODS, AND SYSTEMS FOR GLITCH-FREE CLOCK SWITCHING 有权
    免提时钟切换的设备，方法和系统

    公开(公告)号：US20160269034A1

    公开(公告)日：2016-09-15

    申请号：US14657225

    申请日：2015-03-13

    Applicant: QUALCOMM Incorporated

    Inventor： Chad Everett Winemiller ,  Behnam Amelifard ,  Kenneth Luis Arcudia ,  Jon Raymond Boyette ,  Chia Heng Chang ,  Russell Coleman Deans ,  Kevin Wayne Spears

    IPC: H03L7/08 ,  G06F1/12

    CPC classification number: G06F1/12 ,  G06F1/04 ,  G06F1/3237 ,  G06F1/3293 ,  Y02D10/122 ,  Y02D10/128

    Abstract: Aspects disclosed in the detailed description include apparatuses, methods, and systems for glitch-free clock switching. In this regard, in one aspect, an electronic circuit is switched from a lower-frequency reference clock to a higher-frequency reference clock. An oscillation detection logic is configured to determine the stability of the higher-frequency reference clock prior to switching the electronic circuit to the higher-frequency reference clock. The oscillation detection logic derives a sampled clock signal from the higher-frequency reference clock, wherein the sampled clock signal has a slower frequency than the lower-frequency reference clock. The oscillation detection logic then compares the sampled clock signal against the lower-frequency reference clock to determine the stability of the higher-frequency reference clock. By deterministically detecting stability of a reference clock prior to switching to the reference clock, it is possible to avoid premature switching to an unstable reference clock, thus providing glitch-free clock switching in the electronic circuit.

    Abstract translation: 在详细描述中公开的方面包括用于无毛刺时钟切换的装置，方法和系统。 在这方面，在一个方面，电子电路从低频参考时钟切换到较高频率参考时钟。 振荡检测逻辑被配置为在将电子电路切换到较高频率参考时钟之前确定较高频率参考时钟的稳定性。 振荡检测逻辑从较高频率参考时钟导出采样时钟信号，其中采样时钟信号的频率比低频参考时钟慢。 振荡检测逻辑然后将采样的时钟信号与较低频率参考时钟进行比较，以确定较高频率参考时钟的稳定性。 通过在切换到参考时钟之前确定性地检测参考时钟的稳定性，可以避免过早切换到不稳定的参考时钟，从而在电子电路中提供无毛刺的时钟切换。

    System and method for adjusting clock-data timing in a multi-lane data communication link
    5.
    发明授权
    System and method for adjusting clock-data timing in a multi-lane data communication link 有权

    公开(公告)号：US11115176B1

    公开(公告)日：2021-09-07

    申请号：US16809477

    申请日：2020-03-04

    Applicant: QUALCOMM INCORPORATED

    Inventor： Hadi Goudarzi ,  Chia Heng Chang

    IPC: H04L7/00 ,  G06F13/42 ,  G06F1/3234

    Abstract: Clock-data timing in a multi-lane serial data communication link may be adjusted to compensate for drift. A reference lane may be selected and periodically trained to adjust clock-data timing. In response to initiation of a first lane transitioning from an active state to an inactive state, first information representing the clock-data timing of the reference lane at the time that transition is initiated may be determined. Then, in response to initiation of the first lane transitioning back from the inactive state to the active state, second information representing the clock-data timing of the reference lane at the time that transition is initiated may be determined. The clock-data timing of the first lane may be adjusted based on the first information and the second information.

    Clock data recovery with non-uniform clock tracking
    6.
    发明授权
    Clock data recovery with non-uniform clock tracking 有权

    公开(公告)号：US10084621B2

    公开(公告)日：2018-09-25

    申请号：US15422050

    申请日：2017-02-01

    Applicant: QUALCOMM Incorporated

    Inventor： Yu Song ,  Zhi Zhu ,  Miao Li ,  Li Sun ,  Deqiang Song ,  Chia Heng Chang

    IPC: H03D3/18 ,  H03D3/24 ,  H04L25/03 ,  H04L12/26 ,  H04L27/00

    Abstract: Systems and methods for adjusting a phase step size of a clock data recover (CDR) circuit are described according to aspects of the present disclosure. In certain aspects, a method for adjusting a phase step size of a CDR circuit includes sensing a frequency offset of the CDR circuit, and adjusting the phase step size of the CDR circuit based on the sensed frequency offset. The frequency offset may be sensed by sensing a signal level on an integration path of a loop filter of the CDR circuit. The phase step size of the CDR circuit may be adjusted by switching the CDR circuit between a first phase step size and a second phase step size using a modulator (e.g., a sigma-delta modulator).

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