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    SCANNABLE MEMORIES WITH ROBUST CLOCKING METHODOLOGY TO PREVENT INADVERTENT READS OR WRITES
    1.
    发明申请
    SCANNABLE MEMORIES WITH ROBUST CLOCKING METHODOLOGY TO PREVENT INADVERTENT READS OR WRITES 有权
    具有可靠的时钟方法的扫描存储器，以防止不明朗的读取或写入

    公开(公告)号：US20160078965A1

    公开(公告)日：2016-03-17

    申请号：US14488171

    申请日：2014-09-16

    Applicant: Qualcomm Incorporated

    Inventor： Venugopal Boynapalli ,  Kashyap Ramachandra Bellur ,  Prabaharan Balu ,  Bilal Zafar ,  Alex Dongkyu Park ,  Sei Seung Yoon

    IPC: G11C29/08

    CPC classification number: G11C29/08 ,  G11C8/16 ,  G11C29/20 ,  G11C29/32 ,  G11C2029/3202

    Abstract: An example scannable register file includes a plurality of memory cells and, a shift phase of a scan test shifts data bits from a scan input through the plurality of memory cells to a scan output. The shifting can be performed by, on each clock cycle, reading one of the plurality of memory cells to supply the scan out and writing one of the plurality of memory cells with the data bit on a scan input. To perform sequential reads and writes on each clock cycle, the scannable register can generate a write clock that, during the shift phase, is inverted from the clock used for functional operation. The write clock is generated without glitches so that unintended writes do not occur. Scannable register files can be integrated with scan-based testing (e.g., using automatic test pattern generation) of other modules in an integrated circuit.

    Abstract translation: 示例性可扫描寄存器文件包括多个存储器单元，并且扫描测试的移位阶段将数据位从通过多个存储器单元的扫描输入移位到扫描输出。 可以通过在每个时钟周期读取多个存储器单元中的一个以提供扫描输出并将多个存储器单元中的一个与扫描输入上的数据位一起写入来执行移位。 为了在每个时钟周期执行顺序读取和写入，可扫描寄存器可以产生一个写入时钟，在写入时钟期间，在移位阶段，与用于功能操作的时钟相反。 写时钟不产生毛刺，因此不会发生意外的写入。 可扫描寄存器文件可以集成在集成电路中的其他模块的基于扫描的测试（例如，使用自动测试模式生成）。

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