公开(公告)号：US20160078965A1

公开(公告)日：2016-03-17

申请号：US14488171

申请日：2014-09-16

Applicant: Qualcomm Incorporated

Inventor： Venugopal Boynapalli ,  Kashyap Ramachandra Bellur ,  Prabaharan Balu ,  Bilal Zafar ,  Alex Dongkyu Park ,  Sei Seung Yoon

IPC: G11C29/08

CPC classification number: G11C29/08 ,  G11C8/16 ,  G11C29/20 ,  G11C29/32 ,  G11C2029/3202

Abstract: An example scannable register file includes a plurality of memory cells and, a shift phase of a scan test shifts data bits from a scan input through the plurality of memory cells to a scan output. The shifting can be performed by, on each clock cycle, reading one of the plurality of memory cells to supply the scan out and writing one of the plurality of memory cells with the data bit on a scan input. To perform sequential reads and writes on each clock cycle, the scannable register can generate a write clock that, during the shift phase, is inverted from the clock used for functional operation. The write clock is generated without glitches so that unintended writes do not occur. Scannable register files can be integrated with scan-based testing (e.g., using automatic test pattern generation) of other modules in an integrated circuit.

Abstract translation: 示例性可扫描寄存器文件包括多个存储器单元，并且扫描测试的移位阶段将数据位从通过多个存储器单元的扫描输入移位到扫描输出。 可以通过在每个时钟周期读取多个存储器单元中的一个以提供扫描输出并将多个存储器单元中的一个与扫描输入上的数据位一起写入来执行移位。 为了在每个时钟周期执行顺序读取和写入，可扫描寄存器可以产生一个写入时钟，在写入时钟期间，在移位阶段，与用于功能操作的时钟相反。 写时钟不产生毛刺，因此不会发生意外的写入。 可扫描寄存器文件可以集成在集成电路中的其他模块的基于扫描的测试（例如，使用自动测试模式生成）。

公开(公告)号：US09036446B2

公开(公告)日：2015-05-19

申请号：US13663042

申请日：2012-10-29

Applicant: QUALCOMM Incorporated

Inventor： Esin Terzioglu ,  Changho Jung ,  Shahzad Nazar ,  Balachander Ganesan ,  Alex Dongkyu Park

IPC: G11C8/00 ,  G11C8/10

CPC classification number: G11C8/10

Abstract: A global reset generation method for a pulse latch based pre-decoders in memories that comprises generating a pre-decoded memory address output for a pulse latch circuit, generating a reset signal to reset the pulse latch circuit, providing a combined signal of the pre-decoded memory address output and the reset signal, feeding the combined signal into a low voltage threshold device to manipulate resetting the pulse latch circuit, wherein generating a reset signal comprises generating a reset signal from a matched circuit that is configured to mimic the function of the latch circuit to be reset and wherein generating a reset signal comprises configuring the matched circuit to accommodate a worst case hold pulse delay to allow for resetting the pulse latch before a new clock cycle performs the resetting and having the matched circuit provide the reset signal and a pre-decoded memory address output in the same voltage domain.

Abstract translation: 一种用于存储器中基于脉冲锁存器的预解码器的全局复位产生方法，包括产生用于脉冲锁存电路的预解码存储器地址输出，产生复位信号以复位脉冲锁存电路，提供预处理器的组合信号， 解码的存储器地址输出和复位信号，将组合的信号馈送到低电压阈值器件以操纵复位脉冲锁存电路，其中产生复位信号包括产生来自匹配电路的复位信号，该匹配电路被配置为模拟 锁存电路被复位并且其中产生复位信号包括配置匹配电路以适应最坏情况保持脉冲延迟，以允许在新的时钟周期执行复位之前复位脉冲锁存器并使匹配电路提供复位信号和 在同一电压域内预编译的存储器地址输出。

公开(公告)号：US09330785B1

公开(公告)日：2016-05-03

申请号：US14698844

申请日：2015-04-29

Applicant: QUALCOMM Incorporated

Inventor： Venkatasubramanian Narayanan ,  Keith Alan Bowman ,  Alex Dongkyu Park ,  Francois Ibrahim Atallah

IPC: G11C11/00 ,  G11C29/12 ,  G11C11/419

CPC classification number: G11C11/417 ,  G11C11/419 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50

Abstract: In a static random access memory (SRAM), such as an SRAM cache in a processor or system-on-a-chip (SoC) device, an aging sensor is provided for testing degradation of SRAM cells comprising p-channel metal oxide semiconductor (PMOS) transistors. The minimum power supply voltage VDDMIN for the SRAM may be dynamically scaled up as the SRAM ages by performing read tests with and without the wordline overdrive voltage VWLOD.

Abstract translation: 在诸如处理器或片上系统（SoC）装置中的SRAM缓存的静态随机存取存储器（SRAM）中，提供了老化传感器，用于测试包含p沟道金属氧化物半导体的SRAM单元的劣化 PMOS）晶体管。 SRAM的最小电源电压VDDMIN可以通过执行具有和不具有字线过驱动电压VWLOD的读取测试随SRAM而老化。

公开(公告)号：US20130223178A1

公开(公告)日：2013-08-29

申请号：US13663042

申请日：2012-10-29

Applicant: QUALCOMM Incorporated

Inventor： Esin Terzioglu ,  Changho Jung ,  Shahzad Nazar ,  Balachander Ganesan ,  Alex Dongkyu Park

IPC: G11C8/10

CPC classification number: G11C8/10

Abstract: A global reset generation method for a pulse latch based pre-decoders in memories that comprises generating a pre-decoded memory address output for a pulse latch circuit, generating a reset signal to reset the pulse latch circuit, providing a combined signal of the pre-decoded memory address output and the reset signal, feeding the combined signal into a low voltage threshold device to manipulate resetting the pulse latch circuit, wherein generating a reset signal comprises generating a reset signal from a matched circuit that is configured to mimic the function of the latch circuit to be reset and wherein generating a reset signal comprises configuring the matched circuit to accommodate a worst case hold pulse delay to allow for resetting the pulse latch before a new clock cycle performs the resetting and having the matched circuit provide the reset signal and a pre-decoded memory address output in the same voltage domain.

Abstract translation: 一种用于存储器中基于脉冲锁存器的预解码器的全局复位产生方法，包括产生用于脉冲锁存电路的预解码存储器地址输出，产生复位信号以复位脉冲锁存电路，提供预处理器的组合信号， 解码的存储器地址输出和复位信号，将组合的信号馈送到低电压阈值器件以操纵复位脉冲锁存电路，其中产生复位信号包括产生来自匹配电路的复位信号，该匹配电路被配置为模拟 锁存电路被复位并且其中产生复位信号包括配置匹配电路以适应最坏情况保持脉冲延迟，以允许在新的时钟周期执行复位之前复位脉冲锁存器并使匹配电路提供复位信号和 在同一电压域内预编译的存储器地址输出。

公开(公告)号：US09564210B2

公开(公告)日：2017-02-07

申请号：US14720930

申请日：2015-05-25

Applicant: QUALCOMM Incorporated

Inventor： Venkatasubramanian Narayanan ,  Alex Dongkyu Park

IPC: G11C11/00 ,  G11C11/417 ,  H01L27/11

CPC classification number: G11C11/417 ,  G11C11/419 ,  G11C29/04 ,  G11C29/12005 ,  G11C29/50004 ,  G11C2029/0401 ,  G11C2029/1204 ,  H01L27/1116

Abstract: A static random access memory (SRAM) includes a first bitcell and a second bitcell. The first bitcell includes an aging transistor and the second bitcell includes a non-aging transistor. An aging sensor is coupled between the first bitcell and the second bitcell to determine an amount of aging associated with the aging transistor. In one aspect, the amount of aging associated with the aging transistor is determined based on a difference between a voltage or current associated with the aging transistor and a voltage or current associated with the non-aging transistor.

Abstract translation: 静态随机存取存储器（SRAM）包括第一位单元和第二位单元。 第一位单元包括老化晶体管，第二位单元包括非时效晶体管。 老化传感器耦合在第一位单元和第二位单元之间以确定与老化晶体管相关联的老化量。 在一个方面，与老化晶体管相关联的老化量基于与老化晶体管相关的电压或电流与与非老化晶体管相关联的电压或电流之间的差来确定。

公开(公告)号：US20150279452A1

公开(公告)日：2015-10-01

申请号：US14228091

申请日：2014-03-27

Applicant: QUALCOMM Incorporated

Inventor： Sei Seung YOON ,  Derek Xiaoxiang Yang ,  Alex Dongkyu Park ,  Venkatasubramanian Narayanan

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C7/1057 ,  G11C2207/005

Abstract: A memory and a method for operating the memory having a precharge circuit with inputs of multiple voltage domains are provided. In one aspect, a memory includes a bitline and one or more storage elements coupled to the bitline. The one or more storage elements are configured to operate in a first voltage domain using a first supply voltage. A pull-up circuit is configured to pull up the bitline to a second supply voltage in a second voltage domain. The pull-up circuit is responsive to a first control signal in the first voltage domain and a second control signal in the second voltage domain. The first supply voltage is different than the second supply voltage.

Abstract translation: 提供一种用于操作具有具有多个电压域的输入的预充电电路的存储器的存储器和方法。 在一个方面，存储器包括位线和耦合到位线的一个或多个存储元件。 一个或多个存储元件被配置为使用第一电源电压在第一电压域中操作。 上拉电路被配置为在第二电压域中将位线上拉到第二电源电压。 上拉电路响应于第一电压域中的第一控制信号和第二电压域中的第二控制信号。 第一电源电压不同于第二电源电压。

公开(公告)号：US09666301B2

公开(公告)日：2017-05-30

申请号：US14488171

申请日：2014-09-16

Applicant: QUALCOMM Incorporated

Inventor： Venugopal Boynapalli ,  Kashyap Ramachandra Bellur ,  Prabaharan Balu ,  Bilal Zafar ,  Alex Dongkyu Park ,  Sei Seung Yoon

IPC: G01R31/28 ,  G11C29/08 ,  G11C29/32 ,  G11C8/16 ,  G11C29/20

CPC classification number: G11C29/08 ,  G11C8/16 ,  G11C29/20 ,  G11C29/32 ,  G11C2029/3202

Abstract: An example scannable register file includes a plurality of memory cells and, a shift phase of a scan test shifts data bits from a scan input through the plurality of memory cells to a scan output. The shifting can be performed by, on each clock cycle, reading one of the plurality of memory cells to supply the scan out and writing one of the plurality of memory cells with the data bit on a scan input. To perform sequential reads and writes on each clock cycle, the scannable register can generate a write clock that, during the shift phase, is inverted from the clock used for functional operation. The write clock is generated without glitches so that unintended writes do not occur. Scannable register files can be integrated with scan-based testing (e.g., using automatic test pattern generation) of other modules in an integrated circuit.