公开(公告)号：US20200335151A1

公开(公告)日：2020-10-22

申请号：US16849616

申请日：2020-04-15

Applicant: QUALCOMM Incorporated

Inventor： Chulmin JUNG ,  Keejong KIM ,  Changho JUNG ,  Venugopal BOYNAPALLI

IPC: G11C11/4091 ,  G11C11/4094 ,  G11C11/4099 ,  G11C11/4074 ,  G11C11/408

Abstract: A charge-transfer transistor couples between a bit line and a sense node for a sense amplifier. During a read operation, a charge-transfer driver drives a gate voltage of the charge-transfer transistor to control whether the charge-transfer transistor conducts during a charge-transfer period. Prior to the charge-transfer period, a bitcell is coupled to the bit line to drive a bitcell-effected voltage on to the bit line. The charge-transfer driver drives the gate voltage such that the charge-transfer transistor only conducts when the bitcell-effected voltage equals a pre-charge voltage for the bit line.

公开(公告)号：US20210134358A1

公开(公告)日：2021-05-06

申请号：US17144077

申请日：2021-01-07

Applicant: QUALCOMM Incorporated

Inventor： Changho JUNG ,  Keejong KIM ,  Chulmin JUNG ,  Ritu CHABA

IPC: G11C11/419 ,  G11C7/08 ,  G11C7/10 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/10 ,  G11C11/418

Abstract: A memory is provided that is configured to practice both a conventional normal read operation and also a burst mode read operation. During the normal read operation, the memory pre-charges the bit lines in a group of multiplexed columns. Each column has a sense amplifier that latches a bit decision for the column during the normal read operation. If a subsequent read operation addresses the same group of multiplexed columns, the memory invokes the burst-mode read operation during which the bit lines are not pre-charged.

公开(公告)号：US20170221551A1

公开(公告)日：2017-08-03

申请号：US15013897

申请日：2016-02-02

Applicant: QUALCOMM Incorporated

Inventor： Chulmin JUNG ,  Fahad AHMED ,  Sei Seung YOON ,  Keejong KIM

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C7/02 ,  G11C5/06 ,  G11C7/00 ,  G11C7/062 ,  G11C7/08 ,  G11C7/10 ,  G11C7/14 ,  G11C11/418 ,  G11C11/419 ,  G11C29/02 ,  G11C29/026 ,  G11C29/14 ,  G11C29/50012

Abstract: A memory includes a memory cell, one bitline coupled to the memory cell, a sense amplifier coupled to the one bitline, a timing circuit configured to enable the sense amplifier during a read operation, a control circuit configured to enable the sense amplifier independent of the timing circuit, and a pull-up circuit configured to pull up the one bitline while the sense amplifier is enabled by the control circuit. The method includes enabling a sense amplifier in a read operation by a timing circuit. The sense amplifier is coupled to at least one bitline, and the at least one bitline is coupled to a memory cell. The method further includes enabling the sense amplifier independent of the timing circuit in a second operation and pulling up the at least one bitline by a pull-up circuit while the sense amplifier is enabled in the second operation.

公开(公告)号：US20210280263A1

公开(公告)日：2021-09-09

申请号：US16811145

申请日：2020-03-06

Applicant: QUALCOMM Incorporated

Inventor： Hochul LEE ,  Anil Chowdary KOTA ,  Keejong KIM

IPC: G11C17/18 ,  G11C17/16

Abstract: A One Time Programmable (OTP) memory, includes: a first driver coupled to a reference cell by a first bit line; a second driver coupled to an OTP cell by a second bit line; and a comparator having a first input coupled to the first bit line and the reference cell, a second input coupled to the second bit line and the OTP cell, and an output coupled to a logic circuit configured to control the first driver and the second driver.

公开(公告)号：US20210257007A1

公开(公告)日：2021-08-19

申请号：US16792636

申请日：2020-02-17

Applicant: QUALCOMM Incorporated

Inventor： Anil KOTA ,  Keejong KIM ,  Hochul LEE

IPC: G11C7/06 ,  G11C7/10 ,  G11C17/16 ,  G11C29/14

Abstract: Certain aspects of the present disclosure provide methods and apparatus for testing a one-time programmable (OTP) memory device, including the functionality of a sense amplifier circuit. The OTP memory device includes a memory array, an input latch circuit, and a sense amplifier circuit comprising a current source and a multiplexer. The multiplexer has a first input coupled to an output of the memory array, a second input coupled to the input latch circuit, and an output coupled to an input of the current source circuit.