公开(公告)号：US20190115301A1

公开(公告)日：2019-04-18

申请号：US15913784

申请日：2018-03-06

Applicant: QUALCOMM Incorporated

Inventor： Michael Duane ALSTON ,  Hadi BUNNALIM ,  Lesly Zaren Venturina ENDRINAL ,  Mickael Sebastien Alain MALABRY ,  Lavakumar RANGANATHAN ,  Rami Fathy Amin Gomaa SALEM

IPC: H01L23/544 ,  H01L29/10 ,  H01L29/49 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L21/225 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/66

Abstract: A metal oxide semiconductor (MOS) integrated circuit (IC) has a plurality of fiducial standard cells of different cell sizes. The different cell sizes are non-equally utilized. The plurality of fiducial standard cells are placed to have a random offset from a uniform global placement pattern. Each of the fiducial standard cells has at least four power rails and various sets of active regions. The power rails extend in a first direction. The active regions are provided adjacent to the power rails but are disconnected from contacts and interconnects and thus do not draw power from the power rails. Instead, the active regions are disjoint and collinear thereby creating islands of active regions among spacings of inactive regions. These inactive regions more easily allow electromagnetic radiation to pass through thereby allowing the MOS fiducial standard cell to be visible for a CAD-to-silicon backside image alignment even with 7 nm feature sizes.

公开(公告)号：US20180074117A1

公开(公告)日：2018-03-15

申请号：US15265744

申请日：2016-09-14

Applicant: QUALCOMM Incorporated

Inventor： Rami SALEM ,  Lesly Zaren V. ENDRINAL ,  Hyeokjin LIM ,  Hadi BUNNALIM ,  Robert KIM ,  Lavakumar RANGANATHAN ,  Mickael MALABRY

IPC: G01R31/28 ,  H01L23/50 ,  H01L27/02 ,  H01L27/088 ,  G01R31/311

CPC classification number: G01R31/2891 ,  G01R31/2834 ,  G01R31/311 ,  H01L23/50 ,  H01L23/5286 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/11807 ,  H01L2223/54426

Abstract: A MOS IC includes a first standard cell including first and second power rails, first and second active regions, and a plurality of metal interconnects. The first power rail extends in a first direction and provides a first voltage to the first standard cell. The second power rail extends in the first direction and provides a second voltage to the first standard cell. The first active region is between the first and second power rails on a first side of the first standard cell. The second active region is between the first and second power rails on a second side of the first standard cell. The second active region is separated from the first active region. The plurality of metal interconnects extend in a second direction between the first and second active regions and between the first and second power rails. The second direction is orthogonal to the first direction.

公开(公告)号：US20150380325A1

公开(公告)日：2015-12-31

申请号：US14315324

申请日：2014-06-25

Applicant: QUALCOMM Incorporated

Inventor： Ulrike KINDEREIT ,  Lavakumar RANGANATHAN

IPC: H01L21/66 ,  G01R1/07 ,  H01L27/092

CPC classification number: G01R1/07 ,  G01R31/2884 ,  G01R31/311 ,  H01L22/12 ,  H01L22/24 ,  H01L22/30 ,  H01L27/092

Abstract: An integrated circuit device includes an active silicon layer, and at least one passive metal layer placed in an input region and an output region of the device. The at least one passive metal layer has a surface area and thickness for at least one of the input region or the output region to provide a phase shift of an optical laser, the phase shift corresponding to an optimized visibility of the optical laser during an optic failure analysis of the device.

Abstract translation: 集成电路器件包括有源硅层和放置在器件的输入区域和输出区域中的至少一个无源金属层。 所述至少一个无源金属层具有用于输入区域或输出区域中的至少一个的表面积和厚度以提供光学激光器的相移，所述相移对应于在光学器件期间光学激光器的最佳可见度 设备故障分析