公开(公告)号：US20190115301A1

公开(公告)日：2019-04-18

申请号：US15913784

申请日：2018-03-06

Applicant: QUALCOMM Incorporated

Inventor： Michael Duane ALSTON ,  Hadi BUNNALIM ,  Lesly Zaren Venturina ENDRINAL ,  Mickael Sebastien Alain MALABRY ,  Lavakumar RANGANATHAN ,  Rami Fathy Amin Gomaa SALEM

IPC: H01L23/544 ,  H01L29/10 ,  H01L29/49 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L21/225 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/66

Abstract: A metal oxide semiconductor (MOS) integrated circuit (IC) has a plurality of fiducial standard cells of different cell sizes. The different cell sizes are non-equally utilized. The plurality of fiducial standard cells are placed to have a random offset from a uniform global placement pattern. Each of the fiducial standard cells has at least four power rails and various sets of active regions. The power rails extend in a first direction. The active regions are provided adjacent to the power rails but are disconnected from contacts and interconnects and thus do not draw power from the power rails. Instead, the active regions are disjoint and collinear thereby creating islands of active regions among spacings of inactive regions. These inactive regions more easily allow electromagnetic radiation to pass through thereby allowing the MOS fiducial standard cell to be visible for a CAD-to-silicon backside image alignment even with 7 nm feature sizes.

公开(公告)号：US20180074117A1

公开(公告)日：2018-03-15

申请号：US15265744

申请日：2016-09-14

Applicant: QUALCOMM Incorporated

Inventor： Rami SALEM ,  Lesly Zaren V. ENDRINAL ,  Hyeokjin LIM ,  Hadi BUNNALIM ,  Robert KIM ,  Lavakumar RANGANATHAN ,  Mickael MALABRY

IPC: G01R31/28 ,  H01L23/50 ,  H01L27/02 ,  H01L27/088 ,  G01R31/311

CPC classification number: G01R31/2891 ,  G01R31/2834 ,  G01R31/311 ,  H01L23/50 ,  H01L23/5286 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/11807 ,  H01L2223/54426

Abstract: A MOS IC includes a first standard cell including first and second power rails, first and second active regions, and a plurality of metal interconnects. The first power rail extends in a first direction and provides a first voltage to the first standard cell. The second power rail extends in the first direction and provides a second voltage to the first standard cell. The first active region is between the first and second power rails on a first side of the first standard cell. The second active region is between the first and second power rails on a second side of the first standard cell. The second active region is separated from the first active region. The plurality of metal interconnects extend in a second direction between the first and second active regions and between the first and second power rails. The second direction is orthogonal to the first direction.

公开(公告)号：US20150028495A1

公开(公告)日：2015-01-29

申请号：US14338229

申请日：2014-07-22

Applicant: QUALCOMM Incorporated

Inventor： Xiangdong CHEN ,  Ohsang KWON ,  Esin TERZIOGLU ,  Hadi BUNNALIM

IPC: H01L23/528 ,  H01L23/522

CPC classification number: H01L23/5226 ,  H01L23/498 ,  H01L23/528 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An SOC apparatus includes a plurality of gate interconnects with a minimum pitch g, a plurality of metal interconnects with a minimum pitch m, and a plurality of vias interconnecting the gate interconnects and the metal interconnects. The vias have a minimum pitch v. The values m, g, and v are such that g2+m2≧V2 and an LCM of g and m is less than 20 g. The SOC apparatus may further include a second plurality of metal interconnects with a minimum pitch of m2, where m2>m and the LCM of g, m, and m2 is less than 20 g.

Abstract translation: SOC装置包括具有最小间距g的多个栅极互连，具有最小间距m的多个金属互连以及互连栅极互连和金属互连的多个通孔。 通孔具有最小间距v。值m，g和v使得g2 +m2≥V2，g和m的LCM小于20g。 SOC装置还可以包括具有最小间距m2的第二多个金属互连，其中m2> m且g，m和m2的LCM小于20g。