公开(公告)号：US20160350225A1

公开(公告)日：2016-12-01

申请号：US14726454

申请日：2015-05-29

Applicant: QUALCOMM Incorporated

Inventor： Jason Edward PODAIMA ,  Paul Christopher John WIERCIENSKI ,  Kyle John ERNEWEIN ,  Carlos Javier MOREIRA ,  Meghal VARIA ,  Serag GADELRAB ,  Muhammad Umar CHOUDRY

IPC: G06F12/08 ,  G06F12/10

CPC classification number: G06F12/0862 ,  G06F12/10 ,  G06F12/109 ,  G06F2212/1021 ,  G06F2212/283 ,  G06F2212/312 ,  G06F2212/507 ,  G06F2212/6026 ,  G06F2212/608 ,  G06F2212/65 ,  G06F2212/654

Abstract: Systems and methods for pre-fetching address translations in a memory management unit (MMU) are disclosed. The MMU detects a triggering condition related to one or more translation caches associated with the MMU, the triggering condition associated with a trigger address, generates a sequence descriptor describing a sequence of address translations to pre-fetch into the one or more translation caches, the sequence of address translations comprising a plurality of address translations corresponding to a plurality of address ranges adjacent to an address range containing the trigger address, and issues an address translation request to the one or more translation caches for each of the plurality of address translations, wherein the one or more translation caches pre-fetch at least one address translation of the plurality of address translations into the one or more translation caches when the at least one address translation is not present in the one or more translation caches.

Abstract translation: 公开了用于在存储器管理单元（MMU）中预取地址转换的系统和方法。 MMU检测与与MMU相关联的一个或多个翻译高速缓存相关联的触发条件，与触发地址相关联的触发条件，生成描述地址转换序列以预取到一个或多个翻译高速缓存中的序列描述符， 地址转换序列包括对应于与包含触发地址的地址范围相邻的多个地址范围的多个地址转换，并且向多个地址转换中的每一个的一个或多个翻译高速缓存发出地址转换请求，其中 当所述一个或多个翻译高速缓存中不存在所述至少一个地址转换时，所述一个或多个翻译高速缓冲存储器将所述多个地址转换的至少一个地址转换预取到所述一个或多个翻译高速缓存中。

公开(公告)号：US20160350234A1

公开(公告)日：2016-12-01

申请号：US14859351

申请日：2015-09-20

Applicant: QUALCOMM Incorporated

Inventor： Jason Edward PODAIMA ,  Paul Christopher John WIERCIENSKI ,  Carlos Javier MOREIRA ,  Alexander MIRETSKY ,  Meghal VARIA ,  Kyle John ERNEWEIN ,  Manokanthan SOMASUNDARAM ,  Muhammad Umar CHOUDRY ,  Serag Monier GADELRAB

IPC: G06F12/10 ,  G06F12/08

CPC classification number: G06F12/1063 ,  G06F12/0806 ,  G06F12/0842 ,  G06F12/0844 ,  G06F12/0891 ,  G06F12/1009 ,  G06F12/1036 ,  G06F2212/1024 ,  G06F2212/50 ,  G06F2212/655 ,  G06F2212/682 ,  G06F2212/683 ,  G06F2212/684

Abstract: Systems and methods relate to performing address translations in a multithreaded memory management unit (MMU). Two or more address translation requests can be received by the multithreaded MMU and processed in parallel to retrieve address translations to addresses of a system memory. If the address translations are present in a translation cache of the multithreaded MMU, the address translations can be received from the translation cache and scheduled for access of the system memory using the translated addresses. If there is a miss in the translation cache, two or more address translation requests can be scheduled in two or more translation table walks in parallel.

Abstract translation: 系统和方法涉及在多线程存储器管理单元（MMU）中执行地址转换。 可以由多线程MMU接收两个或多个地址转换请求并并行处理以将地址转换检索到系统存储器的地址。 如果地址转换存在于多线程MMU的转换高速缓存中，则可以从转换高速缓存接收地址转换，并且使用转换的地址来调度系统存储器的访问。 如果翻译缓存中存在缺失，则两个或多个地址转换请求可以在两个或多个平移的平移表中进行调度。