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    CONCURRENT OPTIMIZATION OF MACHINE LEARNING MODEL PERFORMANCE
    1.
    发明申请
    CONCURRENT OPTIMIZATION OF MACHINE LEARNING MODEL PERFORMANCE 有权

    公开(公告)号：US20210019652A1

    公开(公告)日：2021-01-21

    申请号：US16515711

    申请日：2019-07-18

    Applicant: QUALCOMM Incorporated

    Inventor： Serag GADELRAB ,  James ESLIGER ,  Meghal VARIA ,  Kyle ERNEWEIN ,  Alwyn DOS REMEDIOS ,  George LEE

    IPC: G06N20/00 ,  G06N5/04 ,  G06F11/34

    Abstract: Certain aspects of the present disclosure provide techniques for concurrently performing inferences using a machine learning model and optimizing parameters used in executing the machine learning model. An example method generally includes receiving a request to perform inferences on a data set using the machine learning model and performance metric targets for performance of the inferences. At least a first inference is performed on the data set using the machine learning model to meet a latency specified for generation of the first inference from receipt of the request. While performing the at least the first inference, operational parameters resulting in inference performance approaching the performance metric targets are identified based on the machine learning model and operational properties of the computing device. The identified operational parameters are applied to performance of subsequent inferences using the machine learning model.

    CONCURRENT OPTIMIZATION OF MACHINE LEARNING MODEL PERFORMANCE
    3.
    发明公开
    CONCURRENT OPTIMIZATION OF MACHINE LEARNING MODEL PERFORMANCE 审中-公开

    公开(公告)号：US20240112090A1

    公开(公告)日：2024-04-04

    申请号：US18539022

    申请日：2023-12-13

    Applicant: QUALCOMM Incorporated

    Inventor： Serag GADELRAB ,  James Lyall ESLIGER ,  Meghal VARIA ,  Kyle ERNEWEIN ,  Alwyn DOS REMEDIOS ,  George LEE

    IPC: G06N20/00 ,  G06F11/34 ,  G06N5/04

    CPC classification number: G06N20/00 ,  G06F11/3466 ,  G06N5/04

    Abstract: Certain aspects of the present disclosure provide techniques for concurrently performing inferences using a machine learning model and optimizing parameters used in executing the machine learning model. An example method generally includes receiving a request to perform inferences on a data set using the machine learning model and performance metric targets for performance of the inferences. At least a first inference is performed on the data set using the machine learning model to meet a latency specified for generation of the first inference from receipt of the request. While performing the at least the first inference, operational parameters resulting in inference performance approaching the performance metric targets are identified based on the machine learning model and operational properties of the computing device. The identified operational parameters are applied to performance of subsequent inferences using the machine learning model.

    SPECULATIVE PRE-FETCH OF TRANSLATIONS FOR A MEMORY MANAGEMENT UNIT (MMU)
    7.
    发明申请
    SPECULATIVE PRE-FETCH OF TRANSLATIONS FOR A MEMORY MANAGEMENT UNIT (MMU) 审中-公开
    用于存储管理单元（MMU）的转换的预测预处理

    公开(公告)号：US20160350225A1

    公开(公告)日：2016-12-01

    申请号：US14726454

    申请日：2015-05-29

    Applicant: QUALCOMM Incorporated

    Inventor： Jason Edward PODAIMA ,  Paul Christopher John WIERCIENSKI ,  Kyle John ERNEWEIN ,  Carlos Javier MOREIRA ,  Meghal VARIA ,  Serag GADELRAB ,  Muhammad Umar CHOUDRY

    IPC: G06F12/08 ,  G06F12/10

    CPC classification number: G06F12/0862 ,  G06F12/10 ,  G06F12/109 ,  G06F2212/1021 ,  G06F2212/283 ,  G06F2212/312 ,  G06F2212/507 ,  G06F2212/6026 ,  G06F2212/608 ,  G06F2212/65 ,  G06F2212/654

    Abstract: Systems and methods for pre-fetching address translations in a memory management unit (MMU) are disclosed. The MMU detects a triggering condition related to one or more translation caches associated with the MMU, the triggering condition associated with a trigger address, generates a sequence descriptor describing a sequence of address translations to pre-fetch into the one or more translation caches, the sequence of address translations comprising a plurality of address translations corresponding to a plurality of address ranges adjacent to an address range containing the trigger address, and issues an address translation request to the one or more translation caches for each of the plurality of address translations, wherein the one or more translation caches pre-fetch at least one address translation of the plurality of address translations into the one or more translation caches when the at least one address translation is not present in the one or more translation caches.

    Abstract translation: 公开了用于在存储器管理单元（MMU）中预取地址转换的系统和方法。 MMU检测与与MMU相关联的一个或多个翻译高速缓存相关联的触发条件，与触发地址相关联的触发条件，生成描述地址转换序列以预取到一个或多个翻译高速缓存中的序列描述符， 地址转换序列包括对应于与包含触发地址的地址范围相邻的多个地址范围的多个地址转换，并且向多个地址转换中的每一个的一个或多个翻译高速缓存发出地址转换请求，其中 当所述一个或多个翻译高速缓存中不存在所述至少一个地址转换时，所述一个或多个翻译高速缓冲存储器将所述多个地址转换的至少一个地址转换预取到所述一个或多个翻译高速缓存中。

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