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公开(公告)号：US20160283384A1
公开(公告)日：2016-09-29
申请号：US14672133
申请日：2015-03-28
Applicant: QUALCOMM Incorporated
Inventor： Jason Edward PODAIMA , Bohuslav RYCHLIK , Paul Christopher John WIERCIENSKI , Kyle John ERNEWEIN , Carlos Javier MOREIRA , Meghal VARIA , Serag GADELRAB
CPC classification number: G06F12/0862 , G06F12/0875 , G06F12/10 , G06F12/1027 , G06F2212/1021 , G06F2212/452 , G06F2212/602 , G06F2212/6028 , G06F2212/654 , G06F2212/684
Abstract: Methods and systems for pre-fetching address translations in a memory management unit (MMU) of a device are disclosed. In an embodiment, the MMU receives a pre-fetch command from an upstream component of the device, the pre-fetch command including an address of an instruction, pre-fetches a translation of the instruction from a translation table in a memory of the device, and stores the translation of the instruction in a translation cache associated with the MMU.
Abstract translation: 公开了用于在设备的存储器管理单元（MMU）中预取地址转换的方法和系统。 在一个实施例中，MMU从设备的上游组件接收预取命令，预取命令包括指令的地址，从设备的存储器中的转换表预取指令的转换 并将指令的转换存储在与MMU相关联的转换高速缓存中。
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2.发明申请公开(公告)号：US20170285705A1
公开(公告)日：2017-10-05
申请号：US15086054
申请日：2016-03-31
Applicant: QUALCOMM Incorporated
Inventor： Jason Edward PODAIMA , Christophe Denis Bernard AVOINNE , Manokanthan SOMASUNDARAM , Sina DENA , Paul Christopher John WIERCIENSKI , Bohuslav RYCHLIK , Steven John HALTER , Jaya Prakash SUBRAMANIAM GANASAN , Myil RAMKUMAR , Dipt Ranjan PAL
CPC classification number: G06F1/266 , G06F1/10 , G06F1/324 , G06F1/3275 , G06F1/3287 , G06F12/08 , G06F2212/1028 , G06F2212/657 , G06F2212/683 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D10/171
Abstract: Methods and systems are disclosed for full-hardware management of power and clock domains related to a distributed virtual memory (DVM) network. An aspect includes transmitting, from a DVM initiator to a DVM network, a DVM operation, broadcasting, by the DVM network to a plurality of DVM targets, the DVM operation, and, based on the DVM operation being broadcasted to the plurality of DVM targets by the DVM network, performing one or more hardware optimizations comprising: turning on a clock domain coupled to the DVM network or a DVM target of the plurality of DVM targets that is a target of the DVM operation, increasing a frequency of the clock domain, turning on a power domain coupled to the DVM target based on the power domain being turned off, or terminating the DVM operation to the DVM target based on the DVM target being turned off.
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3.发明申请MULTI-THREADED TRANSLATION AND TRANSACTION RE-ORDERING FOR MEMORY MANAGEMENT UNITS 有权用于内存管理单元的多线程翻译和交易重新订购公开(公告)号：US20160350234A1
公开(公告)日：2016-12-01
申请号：US14859351
申请日：2015-09-20
Applicant: QUALCOMM Incorporated
Inventor： Jason Edward PODAIMA , Paul Christopher John WIERCIENSKI , Carlos Javier MOREIRA , Alexander MIRETSKY , Meghal VARIA , Kyle John ERNEWEIN , Manokanthan SOMASUNDARAM , Muhammad Umar CHOUDRY , Serag Monier GADELRAB
CPC classification number: G06F12/1063 , G06F12/0806 , G06F12/0842 , G06F12/0844 , G06F12/0891 , G06F12/1009 , G06F12/1036 , G06F2212/1024 , G06F2212/50 , G06F2212/655 , G06F2212/682 , G06F2212/683 , G06F2212/684
Abstract: Systems and methods relate to performing address translations in a multithreaded memory management unit (MMU). Two or more address translation requests can be received by the multithreaded MMU and processed in parallel to retrieve address translations to addresses of a system memory. If the address translations are present in a translation cache of the multithreaded MMU, the address translations can be received from the translation cache and scheduled for access of the system memory using the translated addresses. If there is a miss in the translation cache, two or more address translation requests can be scheduled in two or more translation table walks in parallel.
Abstract translation: 系统和方法涉及在多线程存储器管理单元（MMU）中执行地址转换。 可以由多线程MMU接收两个或多个地址转换请求并并行处理以将地址转换检索到系统存储器的地址。 如果地址转换存在于多线程MMU的转换高速缓存中，则可以从转换高速缓存接收地址转换，并且使用转换的地址来调度系统存储器的访问。 如果翻译缓存中存在缺失，则两个或多个地址转换请求可以在两个或多个平移的平移表中进行调度。
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Patent Agency Ranking
4.发明申请公开(公告)号：US20190324512A1
公开(公告)日：2019-10-24
申请号：US16458940
申请日：2019-07-01
Applicant: QUALCOMM Incorporated
Inventor： Jason Edward PODAIMA , Christophe Denis Bernard AVOINNE , Manokanthan SOMASUNDARAM , Sina DENA , Paul Christopher John WIERCIENSKI , Bohuslav RYCHLIK , Steven John HALTER , Jaya Prakash SUBRAMANIAM GANASAN , Myil RAMKUMAR , Dipti Ranjan PAL
IPC: G06F1/26 , G06F1/3287 , G06F1/324 , G06F1/3234 , G06F1/10
Abstract: Methods and systems are disclosed for full-hardware management of power and clock domains related to a distributed virtual memory (DVM) network. An aspect includes transmitting, from a DVM initiator to a DVM network, a DVM operation, broadcasting, by the DVM network to a plurality of DVM targets, the DVM operation, and, based on the DVM operation being broadcasted to the plurality of DVM targets by the DVM network, performing one or more hardware optimizations comprising: turning on a clock domain coupled to the DVM network or a DVM target of the plurality of DVM targets that is a target of the DVM operation, increasing a frequency of the clock domain, turning on a power domain coupled to the DVM target based on the power domain being turned off, or terminating the DVM operation to the DVM target based on the DVM target being turned off.
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公开(公告)号：US20160306746A1
公开(公告)日：2016-10-20
申请号：US14865965
申请日：2015-09-25
Applicant: QUALCOMM Incorporated
IPC: G06F12/10
CPC classification number: G06F12/1027 , G06F12/0864 , G06F12/0895 , G06F12/1036 , G06F2212/1021 , G06F2212/1041 , G06F2212/1044 , G06F2212/1048 , G06F2212/50 , G06F2212/652 , G06F2212/654 , G06F2212/683
Abstract: A comparand that includes a virtual address is received. Upon determining a match of the comparand to a burst entry tag, a candidate matching translation data unit is selected. The selecting is from a plurality of translation data units associated with the burst entry tag, and is based at least in part on at least one bit of the virtual address. Content of the candidate matching translation data unit is compared to at least a portion of the comparand. Upon a match, a hit is generated.
Abstract translation: 收到包含虚拟地址的比较。 在确定比较与突发条目标签的匹配时，选择候选匹配翻译数据单元。 所述选择来自与所述突发条目标签相关联的多个翻译数据单元，并且至少部分地基于所述虚拟地址的至少一个位。 将候选匹配翻译数据单元的内容与比较的至少一部分进行比较。 比赛结束后，会产生命中。
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公开(公告)号：US20210288660A1
公开(公告)日：2021-09-16
申请号：US17333282
申请日：2021-05-28
Applicant: QUALCOMM Incorporated
Inventor： Clara Ka Wah SUNG , Meghal VARIA , Serag GADELRAB , Cheng-Teh HSIEH , Jason Edward PODAIMA , Victor SZETO , Richard BOISJOLY , Milivoje ALEKSIC , Tom LONGO , In-Suk CHONG
Abstract: Various embodiments include methods and devices for implementing decompression of compressed high dynamic ratio fields. Various embodiments may include receiving compressed first and second sets of data fields, decompressing the first and second compressed sets of data fields to generate first and second decompressed sets of data fields, receiving a mapping for mapping the first and second decompressed sets of data fields to a set of data units, aggregating the first and second decompressed sets of data fields using the mapping to generate a compression block comprising the set of data units.
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公开(公告)号：US20200274549A1
公开(公告)日：2020-08-27
申请号：US16798186
申请日：2020-02-21
Applicant: QUALCOMM Incorporated
Inventor： Clara Ka Wah SUNG , Meghal VARIA , Serag GADELRAB , Cheng-Teh HSIEH , Jason Edward PODAIMA , Victor SZETO , Richard BOISJOLY , Milivoje ALEKSIC , Tom LONGO , In-Suk CHONG
Abstract: Various embodiments include methods and devices for implementing compression of high dynamic ratio fields. Various embodiments may include receiving a compression block having data units, receiving a mapping for the compression block, wherein the mapping is configured to map bits of each data unit to two or more data fields to generate a first set of data fields and a second set of data fields, compressing the first set of data fields together to generate a compressed first set of data fields, and compressing the second set of data fields together to generate a compressed second set of data fields.
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8.发明申请SPECULATIVE PRE-FETCH OF TRANSLATIONS FOR A MEMORY MANAGEMENT UNIT (MMU) 审中-公开用于存储管理单元（MMU）的转换的预测预处理公开(公告)号：US20160350225A1
公开(公告)日：2016-12-01
申请号：US14726454
申请日：2015-05-29
Applicant: QUALCOMM Incorporated
Inventor： Jason Edward PODAIMA , Paul Christopher John WIERCIENSKI , Kyle John ERNEWEIN , Carlos Javier MOREIRA , Meghal VARIA , Serag GADELRAB , Muhammad Umar CHOUDRY
CPC classification number: G06F12/0862 , G06F12/10 , G06F12/109 , G06F2212/1021 , G06F2212/283 , G06F2212/312 , G06F2212/507 , G06F2212/6026 , G06F2212/608 , G06F2212/65 , G06F2212/654
Abstract: Systems and methods for pre-fetching address translations in a memory management unit (MMU) are disclosed. The MMU detects a triggering condition related to one or more translation caches associated with the MMU, the triggering condition associated with a trigger address, generates a sequence descriptor describing a sequence of address translations to pre-fetch into the one or more translation caches, the sequence of address translations comprising a plurality of address translations corresponding to a plurality of address ranges adjacent to an address range containing the trigger address, and issues an address translation request to the one or more translation caches for each of the plurality of address translations, wherein the one or more translation caches pre-fetch at least one address translation of the plurality of address translations into the one or more translation caches when the at least one address translation is not present in the one or more translation caches.
Abstract translation: 公开了用于在存储器管理单元（MMU）中预取地址转换的系统和方法。 MMU检测与与MMU相关联的一个或多个翻译高速缓存相关联的触发条件，与触发地址相关联的触发条件，生成描述地址转换序列以预取到一个或多个翻译高速缓存中的序列描述符， 地址转换序列包括对应于与包含触发地址的地址范围相邻的多个地址范围的多个地址转换，并且向多个地址转换中的每一个的一个或多个翻译高速缓存发出地址转换请求，其中 当所述一个或多个翻译高速缓存中不存在所述至少一个地址转换时，所述一个或多个翻译高速缓冲存储器将所述多个地址转换的至少一个地址转换预取到所述一个或多个翻译高速缓存中。
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