Asymmetric power states on a communication link

    公开(公告)号:US10482048B2

    公开(公告)日:2019-11-19

    申请号:US16376059

    申请日:2019-04-05

    Abstract: Asymmetric power states on a communication link are disclosed. In one aspect, the communication link is a Peripheral Component Interconnect (PCI) express (PCIe) link. PCIe is a point-to-point communication link between two termini. Exemplary aspects of the present disclosure allow the two termini to be in different power states. By allowing the two termini to be in the different power states, an individual terminus may be put into a low-power state even though the other terminus is maintained at a higher-power state. The different power states are enabled by providing switches between a reference clock and respective termini such that the reference clock may selectively be provided to only one terminus of the communication link, allowing that terminus to remain in the higher-power state while the other terminus enters a low-power state that does not require the reference clock.

    Fast link training in embedded systems

    公开(公告)号:US09645959B2

    公开(公告)日:2017-05-09

    申请号:US14598325

    申请日:2015-01-16

    Abstract: Fast link training in embedded systems is disclosed. In one aspect, a host takes advantage of situations in which the host is coupled to one or more static devices through a communication bus. In particular, because the one or more devices are static, the host may be provided with information about the one or more devices before start up, so that when the host does perform a start up, the host already knows which device(s) to expect. Accordingly, the host may directly query the expected device(s), and after receipt of response(s) from the expected device(s), may begin link training the expected device(s). By using the provided information about the expected device(s) in this fashion, the host may bypass or skip an initial signal detection step used by conventional link training processes. Bypassing the initial signal detection step may save time, which in turn saves power.

    ASYMMETRIC POWER STATES ON A COMMUNICATION LINK

    公开(公告)号:US20190236043A1

    公开(公告)日:2019-08-01

    申请号:US16376059

    申请日:2019-04-05

    Abstract: Asymmetric power states on a communication link are disclosed. In one aspect, the communication link is a Peripheral Component Interconnect (PCI) express (PCIe) link. PCIe is a point-to-point communication link between two termini. Exemplary aspects of the present disclosure allow the two termini to be in different power states. By allowing the two termini to be in the different power states, an individual terminus may be put into a low-power state even though the other terminus is maintained at a higher-power state. The different power states are enabled by providing switches between a reference clock and respective termini such that the reference clock may selectively be provided to only one terminus of the communication link, allowing that terminus to remain in the higher-power state while the other terminus enters a low-power state that does not require the reference clock.

    ASYMMETRIC POWER STATES ON A COMMUNICATION LINK

    公开(公告)号:US20180253138A1

    公开(公告)日:2018-09-06

    申请号:US15449209

    申请日:2017-03-03

    Abstract: Asymmetric power states on a communication link are disclosed. In one aspect, the communication link is a Peripheral Component Interconnect (PCI) express (PCIe) link. PCIe is a point-to-point communication link between two termini. Exemplary aspects of the present disclosure allow the two termini to be in different power states. By allowing the two termini to be in the different power states, an individual terminus may be put into a low-power state even though the other terminus is maintained at a higher-power state. The different power states are enabled by providing switches between a reference clock and respective termini such that the reference clock may selectively be provided to only one terminus of the communication link, allowing that terminus to remain in the higher-power state while the other terminus enters a low-power state that does not require the reference clock.

    Asymmetric power states on a communication link

    公开(公告)号:US10365706B2

    公开(公告)日:2019-07-30

    申请号:US15449209

    申请日:2017-03-03

    Abstract: Asymmetric power states on a communication link are disclosed. In one aspect, the communication link is a Peripheral Component Interconnect (PCI) express (PCIe) link. PCIe is a point-to-point communication link between two termini. Exemplary aspects of the present disclosure allow the two termini to be in different power states. By allowing the two termini to be in the different power states, an individual terminus may be put into a low-power state even though the other terminus is maintained at a higher-power state. The different power states are enabled by providing switches between a reference clock and respective termini such that the reference clock may selectively be provided to only one terminus of the communication link, allowing that terminus to remain in the higher-power state while the other terminus enters a low-power state that does not require the reference clock.

    FAST LINK TRAINING IN EMBEDDED SYSTEMS
    6.
    发明申请
    FAST LINK TRAINING IN EMBEDDED SYSTEMS 有权
    嵌入式系统中的快速链接培训

    公开(公告)号:US20160210254A1

    公开(公告)日:2016-07-21

    申请号:US14598325

    申请日:2015-01-16

    Abstract: Fast link training in embedded systems is disclosed. In one aspect, a host takes advantage of situations in which the host is coupled to one or more static devices through a communication bus. In particular, because the one or more devices are static, the host may be provided with information about the one or more devices before start up, so that when the host does perform a start up, the host already knows which device(s) to expect. Accordingly, the host may directly query the expected device(s), and after receipt of response(s) from the expected device(s), may begin link training the expected device(s). By using the provided information about the expected device(s) in this fashion, the host may bypass or skip an initial signal detection step used by conventional link training processes. Bypassing the initial signal detection step may save time, which in turn saves power.

    Abstract translation: 披露了嵌入式系统中的快速链接训练。 在一个方面,主机利用主机通过通信总线耦合到一个或多个静态设备的情况。 特别地,因为一个或多个设备是静态的,所以主机可以在启动之前被提供关于一个或多个设备的信息,使得当主机执行启动时,主机已经知道哪个设备 期望。 因此,主机可以直接查询所期望的设备,并且在从预期设备接收到响应之后,可以开始链接训练期望的设备。 通过以这种方式使用关于预期设备的提供的信息,主机可以绕过或跳过常规链路训练过程所使用的初始信号检测步骤。 绕过初始信号检测步骤可以节省时间,从而节省电力。

Patent Agency Ranking