公开(公告)号：US08890624B2

公开(公告)日：2014-11-18

申请号：US13645277

申请日：2012-10-04

Applicant: QUALCOMM Incorporated

Inventor： Shuo-Wei Chen ,  David Kuochieh Su

IPC: H03L7/085 ,  H03L7/089

CPC classification number: H03L7/0998 ,  H03K3/03 ,  H03K5/133 ,  H03K2005/00032 ,  H03K2005/00052 ,  H03L7/081 ,  H03L7/093 ,  H03L7/0991 ,  H03L7/0995 ,  H03L7/183 ,  H03L7/1974 ,  H03L2207/50

Abstract: A digital fractional PLL introduces an accumulated phase offset before the digital VCO to achieve the fractional part of the division ratio. To provide this phase offset, the digital accumulator can integrate a fractional component Δn. By forcing Δn to zero, the PLL becomes an integer-N PLL. A de-skew timing configuration can be used to remove any time mismatch between integer and fractional counters of the PLL. A digital PLL can merge the function of frequency generation (DVCO) and that of fractional frequency counting into the same circuit block by reusing various phases of the frequency output to generate a fractional frequency count. A digital integer PLL can include a comparator, wherein the feedback loop of this PLL forces the phase difference between the reference clock and feedback signals to approach zero. By changing the duty cycle of feedback signal, the frequency tracking behavior of the loop can be varied.

Abstract translation: 数字分数PLL在数字VCO之前引入累积的相位偏移，以实现分数比的分数部分。 为了提供这种相位偏移，数字累加器可以集成分数分量＆Dgr; n。 通过强制＆Dgr; n为零，PLL变为整数N PLL。 可以使用去偏移时序配置来消除PLL的整数和分数计数器之间的任何时间不匹配。 数字PLL可以通过重新使用频率输出的各个相位来将频率产生（DVCO）的功能和分数频率计数的功能合并到相同的电路块中，以产生分数频率计数。 数字整数PLL可以包括比较器，其中该PLL的反馈环路迫使参考时钟和反馈信号之间的相位差接近零。 通过改变反馈信号的占空比，可以改变回路的频率跟踪行为。

公开(公告)号：US20130027102A1

公开(公告)日：2013-01-31

申请号：US13645277

申请日：2012-10-04

Applicant: QUALCOMM Incorporated

Inventor： Shuo-Wei Chen ,  David Kuochieh Su

IPC: H03L7/089

CPC classification number: H03L7/0998 ,  H03K3/03 ,  H03K5/133 ,  H03K2005/00032 ,  H03K2005/00052 ,  H03L7/081 ,  H03L7/093 ,  H03L7/0991 ,  H03L7/0995 ,  H03L7/183 ,  H03L7/1974 ,  H03L2207/50

Abstract: A digital fractional PLL introduces an accumulated phase offset before the digital VCO to achieve the fractional part of the division ratio. To provide this phase offset, the digital accumulator can integrate a fractional component Δn. By forcing Δn to zero, the PLL becomes an integer-N PLL. A de-skew timing configuration can be used to remove any time mismatch between integer and fractional counters of the PLL. A digital PLL can merge the function of frequency generation (DVCO) and that of fractional frequency counting into the same circuit block by reusing various phases of the frequency output to generate a fractional frequency count. A digital integer PLL can include a comparator, wherein the feedback loop of this PLL forces the phase difference between the reference clock and feedback signals to approach zero. By changing the duty cycle of feedback signal, the frequency tracking behavior of the loop can be varied.

Abstract translation: 数字分数PLL在数字VCO之前引入累积的相位偏移，以实现分数比的分数部分。 为了提供这种相位偏移，数字累加器可以集成分数分量＆Dgr; n。 通过强制＆Dgr; n为零，PLL变为整数N PLL。 可以使用去偏移时序配置来消除PLL的整数和分数计数器之间的任何时间不匹配。 数字PLL可以通过重新使用频率输出的各个相位来将频率产生（DVCO）的功能和分数频率计数的功能合并到相同的电路块中，以产生分数频率计数。 数字整数PLL可以包括比较器，其中该PLL的反馈环路迫使参考时钟和反馈信号之间的相位差接近零。 通过改变反馈信号的占空比，可以改变回路的频率跟踪行为。