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公开(公告)号：US20160276932A1
公开(公告)日：2016-09-22
申请号：US14793147
申请日：2015-07-07
Applicant: QUALCOMM Incorporated
Inventor： Stuart Pullen , William Rader
IPC: H02M3/158
CPC classification number: H02M3/158 , H02M1/088 , H02M3/1588 , H02M2001/0032 , H02M2001/0054 , Y02B70/1466 , Y02B70/1491 , Y02B70/16
Abstract: In one embodiment, a method receives a shed comparison signal that is based on a comparison of a voltage detected from a voltage converter to a reference voltage and receives a zero cross signal that indicates whether a current from the voltage converter has crossed zero. The shed comparison signal is sampled for a first number of clock cycles to generate shed comparison sampled values. Also, the zero cross signal is sampled for a second number of clock cycles to generate zero cross sampled values where the second number of clock cycles are less than the first number of clock cycles. The method determines a change between a shed state and an unshed state based on the shed comparison sampled values for the first number of clock cycles or the zero cross sampled values for the second number of clock cycles.
Abstract translation: 在一个实施例中，一种方法接收基于从电压转换器检测到的电压与参考电压的比较的减法比较信号，并接收指示来自电压转换器的电流是否已经超过零的零交叉信号。 针对第一数量的时钟周期采样梭口比较信号以产生舍入比较采样值。 而且，零交叉信号被采样第二数量的时钟周期以产生零交叉采样值，其中第二数量的时钟周期小于第一数量的时钟周期。 该方法基于第一数量的时钟周期的舍弃比较采样值或第二数量的时钟周期的零交叉采样值来确定切换状态和未发送状态之间的变化。
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公开(公告)号：US10523042B2
公开(公告)日：2019-12-31
申请号：US15712770
申请日：2017-09-22
Applicant: QUALCOMM Incorporated
Inventor： Chunping Song , Jialei Xu , Stuart Pullen , Steve Hawley , Neal Horovitz , Shashank Prakash Mane
Abstract: Certain aspects of the present disclosure generally relate to reducing the size of parallel charging circuits for charging a battery in a portable device, while still effectively providing input current sensing and reverse current blocking capabilities. One example battery charging circuit generally includes: (1) a first charging circuit comprising a first charging output connectable to a battery and a first converter to provide power to the first charging output; and (2) a second charging circuit comprising a second charging output connectable to the battery, a second converter to provide power to the second charging output, a first transistor coupled between an output of the second converter and the second charging output, and a current-sensing circuit coupled to the output of the second converter to sense a current through the first transistor.
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公开(公告)号：US10270342B2
公开(公告)日：2019-04-23
申请号：US15973787
申请日：2018-05-08
Applicant: QUALCOMM Incorporated
Inventor： Stuart Pullen , Michael Bui , Chunping Song , Jialei Xu
Abstract: Certain aspects of the present disclosure provide methods and apparatus for current sensing and error correction, or at least adjustment, for a switching regulator. One example current-sensing circuit generally includes a first amplifier, a buffer, a low-pass filter, a first switch coupled between an output of the first amplifier and an input of the buffer, a second switch coupled between the output of the first amplifier and an input of the low-pass filter, a third switch coupled between an output of the buffer and the input of the low-pass filter, and a fourth switch coupled between the input of the low-pass filter and a reference node for the circuit.
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公开(公告)号：US09755514B2
公开(公告)日：2017-09-05
申请号：US14793147
申请日：2015-07-07
Applicant: QUALCOMM Incorporated
Inventor： Stuart Pullen , William Rader
CPC classification number: H02M3/158 , H02M1/088 , H02M3/1588 , H02M2001/0032 , H02M2001/0054 , Y02B70/1466 , Y02B70/1491 , Y02B70/16
Abstract: In one embodiment, a method receives a shed comparison signal that is based on a comparison of a voltage detected from a voltage converter to a reference voltage and receives a zero cross signal that indicates whether a current from the voltage converter has crossed zero. The shed comparison signal is sampled for a first number of clock cycles to generate shed comparison sampled values. Also, the zero cross signal is sampled for a second number of clock cycles to generate zero cross sampled values where the second number of clock cycles are less than the first number of clock cycles. The method determines a change between a shed state and an unshed state based on the shed comparison sampled values for the first number of clock cycles or the zero cross sampled values for the second number of clock cycles.
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公开(公告)号：US11557964B2
公开(公告)日：2023-01-17
申请号：US17334642
申请日：2021-05-28
Applicant: Qualcomm Incorporated
Inventor： Stuart Pullen , Jialei Xu , Chunping Song , Ta-Tung Yen
Abstract: An apparatus is disclosed for operating a charge pump in a high-efficiency low-ripple burst mode. In an example aspect, the apparatus includes a charge pump with a flying capacitor, a switching circuit, and a burst-mode controller. The switching circuit is coupled to the flying capacitor and configured to selectively: be in a burst configuration to charge and discharge the flying capacitor based on a clock signal; or be in a pulse-skipping configuration. The burst-mode controller is coupled to the switching circuit and configured to trigger the switching circuit to transition from the pulse-skipping configuration to the burst configuration at a time that occurs between rising edges of the clock signal. The burst-mode controller is also configured to cause charging of the flying capacitor to occur for approximately half a period of the clock signal responsive to triggering the switching circuit to transition from the pulse-skipping configuration to the burst configuration.
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Patent Agency Ranking
公开(公告)号：US20200076306A1
公开(公告)日：2020-03-05
申请号：US16556068
申请日：2019-08-29
Applicant: QUALCOMM Incorporated
Inventor： Stuart Pullen , William Rader
Abstract: A buck-or-boost switching regulator circuit includes an analog control circuit that generates a control signal to control the buck-or-boost switching regulator circuit to operate in different modes including a buck mode, a boost mode, and a pass mode. A first amplifier in the control loop circuit generates a first error signal based on one or more of an output voltage, an input current and an output current of the buck-or-boost switching regulator, and a reference voltage. The control signal is based on the first error signal. A control signal adjustment circuit, coupled to an output of the first amplifier, prevents the control signal from getting high enough to be sliced by a boost voltage ramp signal or to be low enough to be sliced by a buck voltage ramp signal based on an input voltage and an output voltage of the buck-or-boost switching regulator circuit.
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7.发明授权Correction circuits for successive-approximation-register analog-to-digital converters 有权用于逐次逼近寄存器模数转换器的校正电路公开(公告)号：US09294110B1
公开(公告)日：2016-03-22
申请号：US14608928
申请日：2015-01-29
Applicant: QUALCOMM Incorporated
Inventor： Stuart Pullen , William Rader
CPC classification number: H02M3/157 , G01R19/0092 , H03M1/129 , H03M1/46 , H03M1/765
Abstract: In one embodiment, a correction circuit comprises circuit comprises a replica transistor biased at a current density to match that of a high side transistor of an output power switch at a specific load. A sample and hold circuit is coupled to the replica transistor to sample a voltage across the replica transistor. A differential amplifier provides a level shifted differential replica voltage to a tap of a resistor ladder of a successive approximation register analog-to-digital converter in response to the sampled voltage across the replica transistor. A current source provides a current to a top of the resistor ladder.
Abstract translation: 在一个实施例中，校正电路包括电路，其包括以电流密度偏置以与特定负载下的输出功率开关的高侧晶体管相匹配的复制晶体管。 采样和保持电路耦合到复制晶体管以对复制晶体管两端的电压进行采样。 差分放大器响应于复制晶体管上的采样电压，向逐次逼近寄存器模数转换器的电阻梯的抽头提供电平移位差分复制电压。 电流源向电阻梯的顶部提供电流。
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公开(公告)号：US20210376719A1
公开(公告)日：2021-12-02
申请号：US17334642
申请日：2021-05-28
Applicant: Qualcomm Incorporated
Inventor： Stuart Pullen , Jialei Xu , Chunping Song , Ta-Tung Yen
Abstract: An apparatus is disclosed for operating a charge pump in a high-efficiency low-ripple burst mode. In an example aspect, the apparatus includes a charge pump with a flying capacitor, a switching circuit, and a burst-mode controller. The switching circuit is coupled to the flying capacitor and configured to selectively: be in a burst configuration to charge and discharge the flying capacitor based on a clock signal; or be in a pulse-skipping configuration. The burst-mode controller is coupled to the switching circuit and configured to trigger the switching circuit to transition from the pulse-skipping configuration to the burst configuration at a time that occurs between rising edges of the clock signal. The burst-mode controller is also configured to cause charging of the flying capacitor to occur for approximately half a period of the clock signal responsive to triggering the switching circuit to transition from the pulse-skipping configuration to the burst configuration.
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公开(公告)号：US10756614B2
公开(公告)日：2020-08-25
申请号：US16004536
申请日：2018-06-11
Applicant: QUALCOMM Incorporated
Inventor： Stuart Pullen , Michael Bui , Steve Hawley , Chunping Song
Abstract: Methods and apparatus for current sensing and error correction in a switched-mode power supply composed of a high-side transistor coupled to a low-side transistor are described. One example method generally includes capturing a current associated with the low-side transistor at a first time corresponding to the low-side transistor turning off; capturing a current associated with the high-side transistor at a second time corresponding to a first delay after the high-side transistor turns on; capturing the current associated with the high-side transistor at a third time corresponding to the high-side transistor turning off; and applying a first correction current to a current-summing node of the current-sensing circuit for a first interval based on the first delay, wherein the first correction current is based on the captured current associated with the low-side transistor at the first time and on the captured current associated with the high-side transistor at the second time.
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10.发明授权公开(公告)号：US10326296B2
公开(公告)日：2019-06-18
申请号：US15273517
申请日：2016-09-22
Applicant: QUALCOMM Incorporated
Inventor： Stuart Pullen , Steve Hawley , Thomas O'Brien
Abstract: A multi-phase (e.g., dual-phase) concurrent configuration of a power management component supports higher current levels to peripheral devices while maintaining acceptable thermal limits. A dual-phase integrated circuit (IC) having a first input/output (I/O) port coupled to a battery and a second I/O port coupled to an adapter and a peripheral device implements the configuration. The dual phase IC includes a dual-phase voltage regulator that selectively provide power (i) from the first I/O port to the second I/O port to provide power to the peripheral device or (ii) from the second I/O port to the first I/O port to provide power to the battery. A controller activates a boost phase to power the second I/O port in response to detecting a demand current of the peripheral device exceeds a maximum current available from the adapter.
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