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    TECHNIQUES FOR ESTIMATING POWER CONSUMPTION OF A CHIPSET
    2.
    发明申请
    TECHNIQUES FOR ESTIMATING POWER CONSUMPTION OF A CHIPSET 有权

    公开(公告)号：US20220147133A1

    公开(公告)日：2022-05-12

    申请号：US17520388

    申请日：2021-11-05

    申请人： QUALCOMM Incorporated

    发明人： Suyash Ranjan ,  Jittra Jootar ,  Shriram Gurumoorthy ,  Saikat Das

    IPC分类号： G06F1/3234 ,  G06F1/3228 ,  H04W52/02

    摘要： Methods, systems, and devices for wireless communications are described. A device may identify modes from a set of modes in which at least one modem functional block of a set of modem functional blocks of a chipset operates during a portion of a time interval. Each modem functional block may include a set of units classified to have a power response that satisfies a power trend metric for at least one mode. The device may select power calculation equations from a set of power calculation equations based on the set of multiple modes, calculate an power consumption level for the chipset for the time interval based on the selected power calculation equations and a proportion of the time interval a respective multiple modem functional block of the set of modem functional blocks operates in a respective mode of the set of multiple modes.

    Timing calibration control in extended discontinuous reception
    3.
    发明授权
    Timing calibration control in extended discontinuous reception 有权

    公开(公告)号：US10390305B1

    公开(公告)日：2019-08-20

    申请号：US15981737

    申请日：2018-05-16

    申请人： QUALCOMM Incorporated

    发明人： James Francis Geekie ,  Suyash Ranjan ,  Xu Chi

    IPC分类号： H04L12/28 ,  H04W52/02 ,  H04W56/00 ,  H04L29/08

    摘要： Methods, systems, and devices for wireless communication in a user equipment (UE) are described in which a cycle duration of an extended discontinuous reception (eDRX) cycle is determined. The UE enters a sleep state of the eDRX cycle and, based on the determination of the cycle duration, uses a first clock as a timer during the sleep state and uses a second clock as a timing calibrator during the sleep state. The first clock may have a lower power consumption and a higher frequency error, and the second clock may have a higher power consumption and a lower frequency error.