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公开(公告)号：US10915490B2
公开(公告)日：2021-02-09
申请号：US16269636
申请日：2019-02-07
发明人： Neven Klacar , Murali Krishna , Arunn Coimbatore Krishnamurthy , Jitendra Prasad , Jean-Marie Quoc Danh Tran
摘要： Systems and methods for providing audio streams over peripheral component interconnect (PCI) express (PCIE) links are disclosed. In particular, exemplary aspects of the present disclosure are used to calculate an uplink timing requirement and adjust a margin time before a modem encodes audio data so that the encoding is done before data is transmitted to an external network. Further aspects of the present disclosure allow a first integrated circuit (IC) to synchronize its clock with that of the modem.
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2.发明授权公开(公告)号：US11073894B2
公开(公告)日：2021-07-27
申请号：US15931307
申请日：2020-05-13
IPC分类号： G06F1/3234 , G06F13/42
摘要： Systems and methods for power management for Peripheral Component Interconnect express (PCIE) devices allow PCIE termini to enter advanced low-power states while a PCIE link is idle. These advanced low-power states may include scaling a clock frequency up through a complete shutdown of power rails and clocks within the PCIE terminus. Additionally, use of a wakeup signal such as a clock request (CLKREQ or CLKREQ #) signal may allow the terminus to wake relatively quickly and resume operation so as to avoid degradation of the user experience or loss of data.
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公开(公告)号：US10539996B2
公开(公告)日：2020-01-21
申请号：US15798778
申请日：2017-10-31
发明人： Sandip HomChaudhuri , Douglas Dahlby , Murali Krishna , Harinder Singh , Ravi Konda , BalaSubrahmanyam Chintamneedi
IPC分类号： G06F9/00 , G06F1/3234 , G06N20/00 , G06N7/00 , H04W52/02 , G06F1/3287 , G06F1/3293 , G06F1/3296 , G06F9/4401 , G06F12/1009 , G06F13/42 , G06F12/02 , G06F12/123 , G06F12/0862 , G06F12/128 , G06N3/04 , G06N3/08
摘要： The disclosure relates to minimizing power consumption of a WiFi system-on-chip (SOC) during idle periods. The disclosed architecture includes memory banks for the WiFi SoC's embedded processor that can be independently powered on/off and a Memory Management Unit (MMU) to translate virtual addresses to physical addresses and generate exceptions to process accesses to virtual addresses without a corresponding physical address. The architecture can implement a demand paging scheme whereby a MMU fault from an access to code/data not within the embedded memory causes the processor to fetch the code/data from an off-chip secondary memory. To minimize page faults, the architecture stores WiFi client code/data within the embedded processor's memory that is repeatedly accessed with a short periodicity or where there is an intolerance for delays of accessing the code/data.
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公开(公告)号：US20170280385A1
公开(公告)日：2017-09-28
申请号：US15465984
申请日：2017-03-22
CPC分类号： H04W52/0209 , G06F1/324 , G06F1/3253 , G06F1/3296 , G06F13/4278 , H04L41/083 , H04L41/0833 , Y02D10/14 , Y02D10/151 , Y02D70/1262 , Y02D70/142 , Y02D70/164 , Y02D70/26
摘要： Link speed control systems for power optimization are disclosed. In one aspect, a communication link adjusts a data transfer speed based on link utilization levels. In a second exemplary aspect, one or more conditions affecting a link speed are weighted and collectively evaluated to determine an efficient or optimal link speed. By adjusting the link speed in this fashion, lower link speeds may be used, and net power savings may be effectuated.
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5.发明授权公开(公告)号：US10482050B2
公开(公告)日：2019-11-19
申请号：US15722783
申请日：2017-10-02
发明人： Neven Klacar , Yan He , Murali Krishna
摘要： Link role determination in a dual-mode Peripheral Component Interconnect express (PCIe) device is disclosed. In this regard, determining a link role for a dual-mode PCIe device involves configuring the dual-mode PCIe device to operate in a root complex (RC) mode or an endpoint mode. The dual-mode PCIe device first performs a configuration and initiation sequence on a wire-based PCIe link in the RC mode. If the configuration and initiation sequence on the wire-based PCIe link is unsuccessful, then the dual-mode PCIe device invokes a random delay and switches to the endpoint mode at expiration of the random delay. By determining a link role of the dual-mode PCIe device based on the configuration and initiation sequence, it is possible to configure dynamically the dual-mode PCIe device to operate in the RC mode or the endpoint mode, thus allowing flexible configuration of the dual-mode PCIe device based on various application scenarios.
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公开(公告)号：US11815976B2
公开(公告)日：2023-11-14
申请号：US15931409
申请日：2020-05-13
IPC分类号： G06F1/3234 , G06F13/42
CPC分类号： G06F1/3253 , G06F13/4282 , G06F2213/0026
摘要： A system includes an interface circuit configured to provide an interface with a link, and a controller. The controller is configured to receive one or more bandwidth requests from one or more clients, and determine at least one of a link speed and a link width for the link based on the one or more bandwidth requests.
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7.发明申请公开(公告)号：US20180129623A1
公开(公告)日：2018-05-10
申请号：US15722783
申请日：2017-10-02
发明人： Neven Klacar , Yan He , Murali Krishna
CPC分类号： G06F13/4027 , G06F13/385 , G06F13/4282 , G06F2213/0026
摘要： Link role determination in a dual-mode Peripheral Component Interconnect express (PCIe) device is disclosed. In this regard, determining a link role for a dual-mode PCIe device involves configuring the dual-mode PCIe device to operate in a root complex (RC) mode or an endpoint mode. The dual-mode PCIe device first performs a configuration and initiation sequence on a wire-based PCIe link in the RC mode. If the configuration and initiation sequence on the wire-based PCIe link is unsuccessful, then the dual-mode PCIe device invokes a random delay and switches to the endpoint mode at expiration of the random delay. By determining a link role of the dual-mode PCIe device based on the configuration and initiation sequence, it is possible to configure dynamically the dual-mode PCIe device to operate in the RC mode or the endpoint mode, thus allowing flexible configuration of the dual-mode PCIe device based on various application scenarios.
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8.发明申请公开(公告)号：US20200371578A1
公开(公告)日：2020-11-26
申请号：US15931307
申请日：2020-05-13
IPC分类号： G06F1/3234 , G06F13/42
摘要： Systems and methods for power management for Peripheral Component Interconnect express (PCIE) devices allow PCIE termini to enter advanced low-power states while a PCIE link is idle. These advanced low-power states may include scaling a clock frequency up through a complete shutdown of power rails and clocks within the PCIE terminus. Additionally, use of a wakeup signal such as a clock request (CLKREQ or CLKREQ#) signal may allow the terminus to wake relatively quickly and resume operation so as to avoid degradation of the user experience or loss of data.
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公开(公告)号：US20200008144A1
公开(公告)日：2020-01-02
申请号：US16564429
申请日：2019-09-09
IPC分类号： H04W52/02 , G06F1/3296 , H04L12/24
摘要： Link speed control systems for power optimization are disclosed. In one aspect, a communication link adjusts a data transfer speed based on link utilization levels. In a second exemplary aspect, one or more conditions affecting a link speed are weighted and collectively evaluated to determine an efficient or optimal link speed. By adjusting the link speed in this fashion, lower link speeds may be used, and net power savings may be effectuated.
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公开(公告)号：US20190251056A1
公开(公告)日：2019-08-15
申请号：US16269636
申请日：2019-02-07
发明人： Neven Klacar , Murali Krishna , Arunn Coimbatore Krishnamurthy , Jitendra Prasad , Jean-Marie Quoc Danh Tran
CPC分类号： G06F13/4291 , G06F2213/0026 , H04J3/0626 , H04J3/0685
摘要： Systems and methods for providing audio streams over peripheral component interconnect (PCI) express (PCIE) links are disclosed. In particular, exemplary aspects of the present disclosure are used to calculate an uplink timing requirement and adjust a margin time before a modem encodes audio data so that the encoding is done before data is transmitted to an external network. Further aspects of the present disclosure allow a first integrated circuit (IC) to synchronize its clock with that of the modem.
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