公开(公告)号：US09088445B2

公开(公告)日：2015-07-21

申请号：US13787926

申请日：2013-03-07

Applicant: QUALCOMM Incorporated

Inventor： Dexter T. Chun ,  Sumeet S. Sethi ,  John D. Eaton ,  Vinodh R. Cuppu ,  Vikram Arora ,  Vaishnav Srinivas ,  Asim Muhammad Muneer ,  Isaac D. Berk

IPC: H03K17/16 ,  H04L25/02 ,  G06F13/40 ,  H03K19/00

CPC classification number: H04L25/0278 ,  G06F13/4086 ,  H03K19/0005 ,  H03K19/017545 ,  Y02D10/14 ,  Y02D10/151

Abstract: A method of controlling signal termination includes providing first logic for selectively terminating signals received at a first device on a bidirectional data bus, providing second logic for selectively terminating signals received at a second device on the bidirectional data bus, sending first signals from the first device to the second device on the bidirectional data bus at a first speed, stopping the sending of the first signals, after stopping the sending of the first signals, enabling the second logic and shifting a reference voltage of the second device from a first level to a second level, after enabling the second logic at the second device, sending second signals from the first device to the second device on the bidirectional data bus at a higher speed, and controlling the first logic based on a speed of signals received at the first device on the bidirectional data bus.

Abstract translation: 一种控制信号终止的方法包括：提供用于选择性地终止在双向数据总线上在第一设备处接收的信号的第一逻辑，提供用于选择性地终止在双向数据总线上的第二设备处接收的信号的第二逻辑，从第一设备发送第一信号 以第一速度传送到双向数据总线上的第二设备，在停止发送第一信号之后停止发送第一信号，使得第二逻辑能够使第二设备的参考电压从第一电平移位到 在第二设备启用第二逻辑之后，以更高的速度在双向数据总线上从第一设备向第二设备发送第二信号，并且基于在第一设备处接收到的信号的速度来控制第一逻辑 在双向数据总线上。

公开(公告)号：US20130061069A1

公开(公告)日：2013-03-07

申请号：US13668764

申请日：2012-11-05

Applicant: Qualcomm Incorporated

Inventor： Steven S. Thomson ,  Ali Iranli ,  Michael J. Drop ,  Vinodh R. Cuppu ,  Christopher Kong Yee Chun ,  Tao Xue ,  Haw-Jing Lo ,  Moinul H. Khan

IPC: G06F1/26

CPC classification number: G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: Devices and methods for monitoring one or more central processing units in real time is disclosed. The method may include monitoring state data associated with the one or more CPUs in real-time, filtering the state data, and at least partially based on filtered state data, selectively altering one or more system settings. A device may include means for monitoring state data associated with the one or more CPUs in real-time, means for filtering the state data, and means for selectively altering one or more system settings at least partially based on filtered state data. A device may also include a sub-sampling circuit configured to receive a hardware core signal from the central processing unit and output a central processing unit state indication, and an infinite impulse response filter connected to the sub-sampling circuit and configured to receive the central processing unit state indication from the sub-sampling circuit.

Abstract translation: 公开了用于实时监控一个或多个中央处理单元的装置和方法。 该方法可以包括：实时地监视与一个或多个CPU相关联的状态数据，过滤状态数据，并且至少部分地基于经过滤的状态数据，选择性地改变一个或多个系统设置。 设备可以包括用于实时监视与一个或多个CPU相关联的状态数据的装置，用于过滤状态数据的装置，以及用于至少部分地基于经过滤的状态数据选择性地改变一个或多个系统设置的装置。 设备还可以包括子采样电路，其被配置为从中央处理单元接收硬件核心信号并输出​​中央处理单元状态指示，以及无限脉冲响应滤波器，连接到子采样电路并被配置为接收中央 来自子采样电路的处理单元状态指示。

公开(公告)号：US09086877B2

公开(公告)日：2015-07-21

申请号：US13668764

申请日：2012-11-05

Applicant: QUALCOMM Incorporated

Inventor： Steven S. Thomson ,  Ali Iranli ,  Michael J. Drop ,  Vinodh R. Cuppu ,  Christopher Kong Yee Chun ,  Tao Xue ,  Haw-Jing Lo ,  Moinul H. Khan

IPC: G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: Devices and methods for monitoring one or more central processing units in real time are disclosed. The method may include monitoring state data associated with the one or more CPUs in real-time, filtering the state data, and at least partially based on filtered state data, selectively altering one or more system settings. A device may include means for monitoring state data associated with the one or more CPUs in real-time, means for filtering the state data, and means for selectively altering one or more system settings at least partially based on filtered state data. A device may also include a sub-sampling circuit configured to receive a hardware core signal from the central processing unit and output a central processing unit state indication, and an infinite impulse response filter connected to the sub-sampling circuit and configured to receive the central processing unit state indication from the sub-sampling circuit.

Abstract translation: 公开了实时监控一个或多个中央处理单元的装置和方法。 该方法可以包括：实时地监视与一个或多个CPU相关联的状态数据，过滤状态数据，并且至少部分地基于经过滤的状态数据，选择性地改变一个或多个系统设置。 设备可以包括用于实时监视与一个或多个CPU相关联的状态数据的装置，用于过滤状态数据的装置，以及用于至少部分地基于经过滤的状态数据选择性地改变一个或多个系统设置的装置。 设备还可以包括子采样电路，其被配置为从中央处理单元接收硬件核心信号并输出​​中央处理单元状态指示，以及无限脉冲响应滤波器，连接到子采样电路并被配置为接收中央 来自子采样电路的处理单元状态指示。

公开(公告)号：US20140253173A1

公开(公告)日：2014-09-11

申请号：US13787926

申请日：2013-03-07

Applicant: QUALCOMM INCORPORATED

Inventor： Dexter T. Chun ,  Sumeet S. Sethi ,  John D. Eaton ,  Vinodh R. Cuppu ,  Vikram Arora ,  Vaishnav Srinivas ,  Muhammad A. Muneer ,  Isaac D. Berk

IPC: H03K19/0175

CPC classification number: H04L25/0278 ,  G06F13/4086 ,  H03K19/0005 ,  H03K19/017545 ,  Y02D10/14 ,  Y02D10/151

Abstract: A method of controlling signal termination includes providing first logic for selectively terminating signals received at a first device on a bidirectional data bus, providing second logic for selectively terminating signals received at a second device on the bidirectional data bus, sending first signals from the first device to the second device on the bidirectional data bus at a first speed, stopping the sending of the first signals, after stopping the sending of the first signals, enabling the second logic and shifting a reference voltage of the second device from a first level to a second level, after enabling the second logic at the second device, sending second signals from the first device to the second device on the bidirectional data bus at a higher speed, and controlling the first logic based on a speed of signals received at the first device on the bidirectional data bus.

Abstract translation: 一种控制信号终止的方法包括：提供用于选择性地终止在双向数据总线上在第一设备处接收的信号的第一逻辑，提供用于选择性地终止在双向数据总线上的第二设备处接收的信号的第二逻辑，从第一设备发送第一信号 以第一速度传送到双向数据总线上的第二设备，在停止发送第一信号之后停止发送第一信号，使得第二逻辑能够使第二设备的参考电压从第一电平移位到 在第二设备启用第二逻辑之后，以更高的速度在双向数据总线上从第一设备向第二设备发送第二信号，并且基于在第一设备处接收到的信号的速度来控制第一逻辑 在双向数据总线上。