公开(公告)号：US09116876B2

公开(公告)日：2015-08-25

申请号：US13718014

申请日：2012-12-18

Applicant: QUALCOMM Incorporated

Inventor： Woo Tag Kang ,  Roberto F. Averbuj ,  Manish Shah

IPC: G06F11/00 ,  G06F11/27 ,  G11C29/12 ,  G11C29/04

CPC classification number: G06F11/27 ,  G11C29/1201 ,  G11C2029/0401

Abstract: Some novel features pertain to a memory controller that includes a memory controller logic, a built-in-self-tester (BIST) logic, and a switch. The memory controller logic is for controlling memory on a memory die. The built-in-self tester (BIST) logic is for testing the memory. The switch is coupled to the BIST logic and the memory. In some implementations, the BIST logic bypasses the memory controller logic when testing the memory by accessing the memory through the switch. The switch may be controlled by the BIST logic. In some implementations, the switch is coupled to the memory controller logic. The switch may control data to the memory that is transmitted from the memory controller logic and the BIST logic based on priority of the data.

Abstract translation: 一些新颖的功能涉及包括存储器控制器逻辑，内置自测试器（BIST）逻辑和开关的存储器控​​制器。 存储器控制器逻辑用于控制存储器管芯上的存储器。 内置自测试器（BIST）逻辑用于测试存储器。 开关耦合到BIST逻辑和存储器。 在一些实现中，当通过通过交换机访问存储器来测试存储器时，BIST逻辑绕过存储器控制器逻辑。 开关可以由BIST逻辑控制。 在一些实现中，开关耦合到存储器控制器逻辑。 交换机可以基于数据的优先级将数据控制到从存储器控制器逻辑和BIST逻辑发送的存储器。

公开(公告)号：US20140065792A1

公开(公告)日：2014-03-06

申请号：US14076395

申请日：2013-11-11

Applicant: QUALCOMM Incorporated

Inventor： Woo Tag Kang ,  Jonghae Kim

IPC: H01L49/02

CPC classification number: H01L28/40 ,  H01L27/0805 ,  H01L27/101

Abstract: Methods and devices related to a plurality of high breakdown voltage embedded capacitors are presented. A semiconductor device may include gate material embedded in an insulator, a plurality of metal contacts, and a plurality of capacitors. The plurality of capacitors may include a lower electrode, a dielectric formed so as to cover a surface of the lower electrode, and an upper electrode formed on the dielectric. Further, the plurality of contacts may connect each of the lower electrodes of the plurality of capacitors to the gate material. The plurality of capacitors may be connected in series via the gate material.

Abstract translation: 提出了与多个高击穿电压嵌入式电容器相关的方法和装置。 半导体器件可以包括嵌入绝缘体中的栅极材料，多个金属触点和多个电容器。 多个电容器可以包括下电极，形成为覆盖下电极的表面的电介质和形成在电介质上的上电极。 此外，多个触点可以将多个电容器中的每个下电极连接到栅极材料。 多个电容器可以经由栅极材料串联连接。

公开(公告)号：US20160064391A1

公开(公告)日：2016-03-03

申请号：US14469341

申请日：2014-08-26

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Woo Tag Kang ,  Changhan Hobie Yun ,  Wei-Chuan Chen

IPC: H01L27/115 ,  G11C11/409 ,  G11C11/22 ,  H01L27/108

CPC classification number: H01L27/11507 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/401 ,  G11C11/409 ,  H01G7/06 ,  H01L27/10805 ,  H01L27/10808 ,  H01L27/10897 ,  H01L27/11512 ,  H01L27/11514 ,  H01L28/91

Abstract: A memory cell includes a capacitor that includes a first metal layer and a second metal layer. The capacitor includes a ferroelectric layer disposed between the first metal layer and the second metal layer. The ferroelectric layer is a single layer of a bi-stable asymmetric crystalline material.

Abstract translation: 存储单元包括包括第一金属层和第二金属层的电容器。 电容器包括设置在第一金属层和第二金属层之间的铁电层。 铁电层是单层双稳态不对称结晶材料。

公开(公告)号：US08889522B2

公开(公告)日：2014-11-18

申请号：US14076395

申请日：2013-11-11

Applicant: QUALCOMM Incorporated

Inventor： Woo Tag Kang ,  Jonghae Kim

IPC: H01L27/04 ,  H01L49/02 ,  H01L27/08 ,  H01L27/10

CPC classification number: H01L28/40 ,  H01L27/0805 ,  H01L27/101

Abstract: Methods and devices related to a plurality of high breakdown voltage embedded capacitors are presented. A semiconductor device may include gate material embedded in an insulator, a plurality of metal contacts, and a plurality of capacitors. The plurality of capacitors may include a lower electrode, a dielectric formed so as to cover a surface of the lower electrode, and an upper electrode formed on the dielectric. Further, the plurality of contacts may connect each of the lower electrodes of the plurality of capacitors to the gate material. The plurality of capacitors may be connected in series via the gate material.

Abstract translation: 提出了与多个高击穿电压嵌入式电容器相关的方法和装置。 半导体器件可以包括嵌入绝缘体中的栅极材料，多个金属触点和多个电容器。 多个电容器可以包括下电极，形成为覆盖下电极的表面的电介质和形成在电介质上的上电极。 此外，多个触点可以将多个电容器中的每个下电极连接到栅极材料。 多个电容器可以经由栅极材料串联连接。