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    Cycling improvement using higher erase bias
    2.
    发明申请
    Cycling improvement using higher erase bias 有权
    使用更高的擦除偏置循环改进

    公开(公告)号：US20080151644A1

    公开(公告)日：2008-06-26

    申请号：US11724711

    申请日：2007-03-16

    申请人： Sheung-Hee Park ,  Xuguang Wang ,  Wing Leung ,  Ming-Sang Kwan ,  Yi He ,  Edward Franklin Runnion

    发明人： Sheung-Hee Park ,  Xuguang Wang ,  Wing Leung ,  Ming-Sang Kwan ,  Yi He ,  Edward Franklin Runnion

    IPC分类号： G11C16/04 ,  G11C11/34

    CPC分类号： G11C16/16 ,  G11C16/14

    摘要： Methods of erasing flash memory cells are provided that improve erase cycling speed and reliability. One embodiment comprises interactively applying a stepped or ramped drain voltage pattern to a drain of the memory cells and a pulsed gate voltage pattern to a gate of the memory cells for a predetermined number of gate pulses or until all the memory cells are erased. In another embodiment, an erase bias circuit is provided for erasing a sector of flash memory cells, the circuit comprising row and column decoders that selects wordline rows and columns of cells, respectively, a supply bias arrangement that provides source and drain supply voltages for the sector, and a patterned pulse bias arrangement configured to provide a pulsed gate voltage pattern to gates of the cells selected by the row decoder and a drain voltage pattern to the drains of the cells selected by the column decoder.

    摘要翻译： 提供了擦除闪存单元的方法，其提高了擦除循环速度和可靠性。 一个实施例包括将阶梯式或倾斜的漏极电压图案交互地施加到存储器单元的漏极，以及脉冲栅极电压图案到达预定数量的栅极脉冲的存储器单元的栅极，或者直到所有存储器单元被擦除。 在另一个实施例中，提供擦除偏置电路用于擦除闪速存储器单元的扇区，该电路包括分别选择字线行和单元列的行和列解码器，该电源偏置装置为 以及图案化脉冲偏压装置，其被配置为向由行解码器选择的单元的栅极和漏极电压图案提供脉冲栅极电压图案到由列解码器选择的单元的漏极。

    Cycling improvement using higher erase bias
    4.
    发明授权
    Cycling improvement using higher erase bias 有权
    使用更高的擦除偏置循环改进

    公开(公告)号：US07561471B2

    公开(公告)日：2009-07-14

    申请号：US11724711

    申请日：2007-03-16

    申请人： Sheung-Hee Park ,  Xuguang Wang ,  Wing Leung ,  Ming-Sang Kwan ,  Yi He ,  Edward Franklin Runnion

    发明人： Sheung-Hee Park ,  Xuguang Wang ,  Wing Leung ,  Ming-Sang Kwan ,  Yi He ,  Edward Franklin Runnion

    IPC分类号： G11C16/16

    CPC分类号： G11C16/16 ,  G11C16/14

    摘要： Methods of erasing flash memory cells are provided that improve erase cycling speed and reliability. One embodiment comprises interactively applying a stepped or ramped drain voltage pattern to a drain of the memory cells and a pulsed gate voltage pattern to a gate of the memory cells for a predetermined number of gate pulses or until all the memory cells are erased. In another embodiment, an erase bias circuit is provided for erasing a sector of flash memory cells, the circuit comprising row and column decoders that selects wordline rows and columns of cells, respectively, a supply bias arrangement that provides source and drain supply voltages for the sector, and a patterned pulse bias arrangement configured to provide a pulsed gate voltage pattern to gates of the cells selected by the row decoder and a drain voltage pattern to the drains of the cells selected by the column decoder.

    摘要翻译： 提供了擦除闪存单元的方法，其提高了擦除循环速度和可靠性。 一个实施例包括将阶梯式或倾斜的漏极电压图案交互地施加到存储器单元的漏极，以及脉冲栅极电压图案到达预定数量的栅极脉冲的存储器单元的栅极，或者直到所有存储器单元被擦除。 在另一个实施例中，提供擦除偏置电路用于擦除闪速存储器单元的扇区，该电路包括分别选择字线行和单元列的行和列解码器，该电源偏置装置为 以及图案化脉冲偏压装置，其被配置为向由行解码器选择的单元的栅极和漏极电压图案提供脉冲栅极电压图案到由列解码器选择的单元的漏极。

    Barrier region underlying source/drain regions for dual-bit memory devices
    6.
    发明授权
    Barrier region underlying source/drain regions for dual-bit memory devices 有权
    用于双位存储器件的源极/漏极区域的屏障区域

    公开(公告)号：US09171936B2

    公开(公告)日：2015-10-27

    申请号：US11634777

    申请日：2006-12-06

    申请人： Shankar Sinha ,  Yi He ,  Zhizheng Liu ,  Ming-Sang Kwan

    发明人： Shankar Sinha ,  Yi He ,  Zhizheng Liu ,  Ming-Sang Kwan

    IPC分类号： H01L29/66 ,  H01L21/265 ,  H01L27/115 ,  H01L29/792

    CPC分类号： H01L29/66833 ,  H01L21/26506 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/792

    摘要： One embodiment of the present invention relates to a memory cell. The memory cell comprises a substrate and a stacked gate structure disposed on the substrate, wherein the stacked gate structure comprises a charge trapping dielectric layer that is adapted to store at least one bit of data. The memory cell further includes a source and drain in the substrate, wherein the source and drain are disposed at opposite sides of the stacked gate structure. A barrier region is disposed substantially beneath the source or the drain and comprises an inert species. Other embodiments are also disclosed.

    摘要翻译： 本发明的一个实施例涉及一种存储单元。 存储单元包括衬底和布置在衬底上的层叠栅极结构，其中堆叠栅极结构包括适于存储至少一位数据的电荷捕获介电层。 存储单元还包括衬底中的源极和漏极，其中源极和漏极设置在堆叠的栅极结构的相对侧。 阻挡区域基本上设置在源极或漏极下方并且包括惰性物质。 还公开了其他实施例。

    Barrier region for memory devices
    7.
    发明申请
    Barrier region for memory devices 有权
    存储设备的屏障区域

    公开(公告)号：US20080135902A1

    公开(公告)日：2008-06-12

    申请号：US11634777

    申请日：2006-12-06

    申请人： Shankar Sinha ,  Yi He ,  Zhizheng Liu ,  Ming-Sang Kwan

    发明人： Shankar Sinha ,  Yi He ,  Zhizheng Liu ,  Ming-Sang Kwan

    IPC分类号： H01L29/94 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

    CPC分类号： H01L29/66833 ,  H01L21/26506 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/792

    摘要： One embodiment of the present invention relates to a memory cell. The memory cell comprises a substrate and a stacked gate structure disposed on the substrate, wherein the stacked gate structure comprises a charge trapping dielectric layer that is adapted to store at least one bit of data. The memory cell further includes a source and drain in the substrate, wherein the source and drain are disposed at opposite sides of the stacked gate structure. A barrier region is disposed substantially beneath the source or the drain and comprises an inert species. Other embodiments are also disclosed.

    摘要翻译： 本发明的一个实施例涉及一种存储单元。 存储单元包括衬底和布置在衬底上的层叠栅极结构，其中堆叠栅极结构包括适于存储至少一位数据的电荷捕获介电层。 存储单元还包括衬底中的源极和漏极，其中源极和漏极设置在堆叠的栅极结构的相对侧。 阻挡区域基本上设置在源极或漏极下方并且包括惰性物质。 还公开了其他实施例。

    Triple well flash memory fabrication process
    8.
    发明授权
    Triple well flash memory fabrication process 失效
    三重闪存制造工艺

    公开(公告)号：US6043123A

    公开(公告)日：2000-03-28

    申请号：US863917

    申请日：1997-05-27

    申请人： Hsingya Arthur Wang ,  Jein-Chen Young ,  Ming-Sang Kwan

    发明人： Hsingya Arthur Wang ,  Jein-Chen Young ,  Ming-Sang Kwan

    IPC分类号： H01L21/8247 ,  H01L27/115

    CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11546

    摘要： A process is described for fabricating an integrated circuit memory in a semiconductor substrate. In the substrate, a first well is formed by introduction of dopant opposite to conductivity of the substrate. Within the first well a second well is formed of conductivity type matching the substrate. The memory cells are fabricated in the second well and have source and drain regions opposite the conductivity type substrate. Each of the first and second wells also includes a region of corresponding conductivity type to enable separate electrical connections to be made to each of the wells.

    摘要翻译： 描述了在半导体衬底中制造集成电路存储器的过程。 在衬底中，通过引入与衬底的导电性相反的掺杂剂形成第一阱。 在第一阱内，第二阱由与衬底相匹配的导电类型形成。 存储单元被制造在第二阱中并且具有与导电类型衬底相对的源区和漏区。 第一和第二孔中的每一个还包括相应导电类型的区域，以使得能够对每个孔进行单独的电连接。

    Thin oxide dummy tiling as charge protection
    9.
    发明授权
    Thin oxide dummy tiling as charge protection 有权
    薄氧化虚拟平铺作为电荷保护

    公开(公告)号：US07977218B2

    公开(公告)日：2011-07-12

    申请号：US11645475

    申请日：2006-12-26

    申请人： Cinti Chen ,  Yi He ,  Wenmei Li ,  Zhizheng Liu ,  Ming-Sang Kwan ,  Yu Sun ,  Jean Yee-Mei Yang

    发明人： Cinti Chen ,  Yi He ,  Wenmei Li ,  Zhizheng Liu ,  Ming-Sang Kwan ,  Yu Sun ,  Jean Yee-Mei Yang

    IPC分类号： H01L21/00

    CPC分类号： H01L27/115 ,  H01L27/0207 ,  H01L27/11568

    摘要： Novel fabrication methods implement the use of dummy tiles to avoid the effects of in-line charging, ESD events, and such charge effects in the formation of a memory device region region. One method involves forming at least a portion of a memory core array upon a semiconductor substrate that involves forming STI structures in the substrate substantially surrounding a memory device region region within the array. An oxide layer is formed over the substrate in the memory device region region and over the STI's, wherein an inner section of the oxide layer formed over the memory device region region is thicker than an outer section of the oxide layer formed over the STI's. A first polysilicon layer is then formed over the inner and outer sections comprising one or more dummy tiles formed over one or more outer sections and electrically connected to at least one inner section.

    摘要翻译： 新颖的制造方法实现使用虚拟瓦片以避免在形成存储器件区域区域中的在线充电，ESD事件和这种电荷效应的影响。 一种方法包括在半导体衬底上形成至少一部分存储器芯阵列，该半导体衬底涉及在衬底中形成基本上围绕阵列内的存储器件区域区域的STI结构。 在存储器件区域和STI之上的衬底上形成氧化物层，其中形成在存储器件区域上的氧化物层的内部部分比在STI上形成的氧化物层的外部部分更厚。 然后在内部和外部部分上形成第一多晶硅层，包括形成在一个或多个外部部分上并且电连接到至少一个内部部分的一个或多个虚拟瓦片。