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    Systems and methods for reducing leakage current in memory arrays
    2.
    发明授权
    Systems and methods for reducing leakage current in memory arrays 有权
    减少存储器阵列泄漏电流的系统和方法

    公开(公告)号：US08861283B1

    公开(公告)日：2014-10-14

    申请号：US13605428

    申请日：2012-09-06

    Applicant: Brian Yung Fun Wong ,  Shankar Sinha ,  Shih-Lin S. Lee ,  Abhishek B. Sharma

    Inventor： Brian Yung Fun Wong ,  Shankar Sinha ,  Shih-Lin S. Lee ,  Abhishek B. Sharma

    IPC: G11C7/00

    CPC classification number: G11C7/12 ,  G11C11/419

    Abstract: Disclosed are apparatus and devices for programming and operating a programmable memory array portion coupled with a leakage reduction circuit. At the leakage reduction circuit, a frame bias signal that indicates a majority state of the memory array portion can be received. During idle states of the programmable memory array portion, at least one shared bit line of the memory array portion can be selectively biased based on the received frame bias signal. In one aspect, a first one of two bit lines is biased to a first state, while the second one of the two bits lines is biased to a second state that is opposite the first state. In a further aspect, the first state is a same state as the majority state of the memory array portion.

    Abstract translation: 公开了用于编程和操作与泄漏减少电路耦合的可编程存储器阵列部分的装置和装置。 在泄漏降低电路中，可以接收指示存储器阵列部分的多数状态的帧偏置信号。 在可编程存储器阵列部分的空闲状态期间，存储器阵列部分的至少一个共享位线可以基于所接收的帧偏置信号被选择性地偏置。 在一个方面，两个位线中的第一位被偏置到第一状态，而两个位线中的第二位被偏置到与第一状态相反的第二状态。 在另一方面，第一状态是与存储器阵列部分的多数状态相同的状态。

    Integrated circuits with asymmetric and stacked transistors
    3.
    发明授权
    Integrated circuits with asymmetric and stacked transistors 有权
    具有不对称和堆叠晶体管的集成电路

    公开(公告)号：US08482963B1

    公开(公告)日：2013-07-09

    申请号：US12629831

    申请日：2009-12-02

    Applicant: Jun Liu ,  Yanzhong Xu ,  Shankar Sinha ,  Shih-Lin S. Lee ,  Jeffrey Xiaoqi Tung ,  Albert Ratnakumar ,  Qi Xiang ,  Irfan Rahim ,  Andy L. Lee ,  Jeffrey T. Watt ,  Srinivas Perisetty

    Inventor： Jun Liu ,  Yanzhong Xu ,  Shankar Sinha ,  Shih-Lin S. Lee ,  Jeffrey Xiaoqi Tung ,  Albert Ratnakumar ,  Qi Xiang ,  Irfan Rahim ,  Andy L. Lee ,  Jeffrey T. Watt ,  Srinivas Perisetty

    IPC: G11C11/00

    CPC classification number: G11C11/412

    Abstract: Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.

    Abstract translation: 不对称晶体管可以通过在晶体管的一个源极 - 漏极端子上而不是另一个产生凹穴注入来形成。 也可以使用具有不同功函数的第一和第二栅极导体的双栅结构来形成非对称晶体管。 可以通过堆叠相同通道类型的两个晶体管串联形成堆叠晶体管。 两个晶体管中的每一个的源极 - 漏极端子之一连接到公共节点。 两个晶体管的栅极也连接在一起。 两个晶体管可以具有不同的阈值电压。 位于堆叠晶体管中较高的晶体管的阈值电压可以具有比堆叠晶体管中的另一个晶体管更低的阈值电压。 堆叠的晶体管可用于减少诸如存储器单元的电路中的漏电流。 不对称晶体管也可用于存储器单元中以减少泄漏。

    Dielectric extension to mitigate short channel effects
    5.
    发明申请
    Dielectric extension to mitigate short channel effects 有权
    电介质延伸以减轻短路效应

    公开(公告)号：US20080157199A1

    公开(公告)日：2008-07-03

    申请号：US11724725

    申请日：2007-03-16

    Applicant: Vidyut Gopal ,  Shankar Sinha ,  Jean Yee-Mei Yang ,  Phillip L. Jones

    Inventor： Vidyut Gopal ,  Shankar Sinha ,  Jean Yee-Mei Yang ,  Phillip L. Jones

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L21/28123 ,  H01L21/31144 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/6653

    Abstract: In patterning a transistor, some of a layer of gate dielectric material is allowed to remain over a semiconductor substrate upon which the transistor is formed. This remaining dielectric material retards the implantation of dopants into the underlying substrate, effectively lengthening a channel region of the transistor. This mitigates unwanted short channel effects, such as leakage currents, for example, and thus mitigates yield loss by establishing a transistor that performs in a more predictable or otherwise desirable manner.

    Abstract translation: 在图案化晶体管时，允许一层栅极电介质材料保留在其上形成晶体管的半导体衬底上。 这种剩余的介电材料阻止掺杂剂注入到下面的衬底中，有效地延长晶体管的沟道区。 这减轻了诸如泄漏电流等不需要的短通道效应，从而通过建立以更可预测或以其它方式所需的方式执行的晶体管来减轻产量损失。

    Using thick spacer for bitline implant then remove
    6.
    发明申请
    Using thick spacer for bitline implant then remove 有权
    使用厚间隔物进行位线植入，然后移除

    公开(公告)号：US20080153223A1

    公开(公告)日：2008-06-26

    申请号：US11724775

    申请日：2007-03-16

    Applicant: Zhizheng Liu ,  Shankar Sinha ,  Timothy Thurgate ,  Ming-Sang Kwan

    Inventor： Zhizheng Liu ,  Shankar Sinha ,  Timothy Thurgate ,  Ming-Sang Kwan

    IPC: H01L21/336 ,  H01L21/8238

    CPC classification number: H01L27/115 ,  H01L27/11568

    Abstract: The present invention pertains to a system method of forming at least a portion of a dual bit memory core array upon a semiconductor substrate, the method comprising forming adjacent first memory cell process assemblies; comprising a charge trapping dielectric, a first polysilicon layer and defining a first bitline opening there between, forming first polysilicon layer features over the charge trapping dielectric layer, depositing a layer of second spacer material over the charge trapping dielectric and the first polysilicon layer features, forming a sidewall spacer adjacent to the charge trapping dielectric and the first polysilicon layer features to define a second bitline opening between the adjacent memory cells, performing a bitline implant, or pocket implants, or both into the bitline opening to establish buried bitlines within the substrate having respective bitline widths that are narrower than the respective widths of the first bitline openings, removing the sidewall spacers, and performing back end processing.

    Abstract translation: 本发明涉及一种在半导体衬底上形成双位存储器芯阵列的至少一部分的系统方法，该方法包括形成相邻的第一存储单元处理组件; 包括电荷捕获电介质，第一多晶硅层并且在其间限定第一位线开口，在电荷俘获电介质层上形成第一多晶硅层特征，在电荷俘获电介质和第一多晶硅层特征之上沉积第二间隔物材料层， 形成与电荷俘获电介质相邻的侧壁间隔物，并且第一多晶硅层的特征在于限定相邻存储器单元之间的第二位线开口，执行位线注入或凹坑注入，或两者进入位线开口以在衬底内建立掩埋位线 具有比第一位线开口的相应宽度窄的各自的位线宽度，去除侧壁间隔件，以及执行后端处理。

    MULTIPORT MEMORY ELEMENT CIRCUITRY
    7.
    发明申请
    MULTIPORT MEMORY ELEMENT CIRCUITRY 有权
    多媒体存储元件电路

    公开(公告)号：US20120311401A1

    公开(公告)日：2012-12-06

    申请号：US13149249

    申请日：2011-05-31

    Applicant: Shih-Lin S. Lee ,  Peter J. McElheny ,  Preminder Singh ,  Shankar Sinha

    Inventor： Shih-Lin S. Lee ,  Peter J. McElheny ,  Preminder Singh ,  Shankar Sinha

    IPC: G11C7/00 ,  G06F11/10 ,  H03M13/05

    CPC classification number: G11C7/00 ,  G06F12/1425 ,  G11C8/16 ,  G11C2029/0411

    Abstract: Integrated circuits with multiport memory elements may be provided. A multiport memory element may include a latching circuit, a first set of address transistors, and a second set of address transistors. The latching circuit may include cross-coupled inverters, each of which includes a pull-up transistor and a pull-down transistor. The first set of address transistors may couple the latching circuit to a write port, whereas the second set of address transistors may couple the latching circuit to a read port. The pull-down transistors and the second set of address transistors may have body bias terminals that are controlled by a control signal. During data loading operations, the control signal may be temporarily elevated to weaken the pull-down transistors and the second set of address transistors to improve the write margin of the multiport memory element.

    Abstract translation: 可以提供具有多端口存储器元件的集成电路。 多端口存储元件可以包括锁存电路，第一组地址晶体管和第二组地址晶体管。 锁存电路可以包括交叉耦合的反相器，每个反相器包括上拉晶体管和下拉晶体管。 第一组地址晶体管可以将锁存电路耦合到写入端口，而第二组地址晶体管可以将锁存电路耦合到读取端口。 下拉晶体管和第二组地址晶体管可以具有由控制信号控制的体偏置端子。 在数据加载操作期间，控制信号可以临时升高以削弱下拉晶体管和第二组地址晶体管，以改善多端口存储器元件的写入裕度。

    Barrier region underlying source/drain regions for dual-bit memory devices
    10.
    发明授权
    Barrier region underlying source/drain regions for dual-bit memory devices 有权
    用于双位存储器件的源极/漏极区域的屏障区域

    公开(公告)号：US09171936B2

    公开(公告)日：2015-10-27

    申请号：US11634777

    申请日：2006-12-06

    Applicant: Shankar Sinha ,  Yi He ,  Zhizheng Liu ,  Ming-Sang Kwan

    Inventor： Shankar Sinha ,  Yi He ,  Zhizheng Liu ,  Ming-Sang Kwan

    IPC: H01L29/66 ,  H01L21/265 ,  H01L27/115 ,  H01L29/792

    CPC classification number: H01L29/66833 ,  H01L21/26506 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/792

    Abstract: One embodiment of the present invention relates to a memory cell. The memory cell comprises a substrate and a stacked gate structure disposed on the substrate, wherein the stacked gate structure comprises a charge trapping dielectric layer that is adapted to store at least one bit of data. The memory cell further includes a source and drain in the substrate, wherein the source and drain are disposed at opposite sides of the stacked gate structure. A barrier region is disposed substantially beneath the source or the drain and comprises an inert species. Other embodiments are also disclosed.

    Abstract translation: 本发明的一个实施例涉及一种存储单元。 存储单元包括衬底和布置在衬底上的层叠栅极结构，其中堆叠栅极结构包括适于存储至少一位数据的电荷捕获介电层。 存储单元还包括衬底中的源极和漏极，其中源极和漏极设置在堆叠的栅极结构的相对侧。 阻挡区域基本上设置在源极或漏极下方并且包括惰性物质。 还公开了其他实施例。

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