公开(公告)号：US07599228B1

公开(公告)日：2009-10-06

申请号：US10976760

申请日：2004-11-01

申请人： Qiang Lu ,  Kuo-Tung Chang ,  Kazuhiro Mizutani ,  Sung-Chul Lee ,  Sheung-Hee Park ,  Ming-Sang Kwan

发明人： Qiang Lu ,  Kuo-Tung Chang ,  Kazuhiro Mizutani ,  Sung-Chul Lee ,  Sheung-Hee Park ,  Ming-Sang Kwan

IPC分类号： G11C16/04

CPC分类号： G11C16/3404

摘要： A memory device is provided including circuitry for correcting an over-erased memory cell in the memory device. The memory device may include a substrate. A control gate and a floating gate may be formed over the substrate. The memory device may include a source region and a drain region. A first resistive element may be coupled between the source region and the control gate.

摘要翻译： 提供了一种存储器件，其包括用于校正存储器件中的擦除过的存储器单元的电路。 存储器件可以包括衬底。 可以在衬底上形成控制栅极和浮置栅极。 存储器件可以包括源极区域和漏极区域。 第一电阻元件可以耦合在源极区域和控制栅极之间。

公开(公告)号：US07952938B2

公开(公告)日：2011-05-31

申请号：US12773232

申请日：2010-05-04

申请人： Gulzar Ahmed Kathawala ,  Wei Zheng ,  Zhizheng Liu ,  Sung-Yong Chung ,  Timothy Thurgate ,  Kuo-Tung Chang ,  Sheung-Hee Park ,  Gabrielle Wing Han Leung

发明人： Gulzar Ahmed Kathawala ,  Wei Zheng ,  Zhizheng Liu ,  Sung-Yong Chung ,  Timothy Thurgate ,  Kuo-Tung Chang ,  Sheung-Hee Park ,  Gabrielle Wing Han Leung

IPC分类号： G11C16/04

CPC分类号： G11C16/3418

摘要： A memory device comprising an optimization component that facilitates erasing memory cells in a substantially homogeneous electromagnetic field and methods that facilitate erasing memory cells in a substantially homogeneous electromagnetic field are presented. The optimization component facilitates selecting a subset of memory cells to be erased at the same time, such that a memory cell in the subset of memory cells has two neighbor memory cells adjacent thereto that are in the subset of memory, or one neighbor memory cell adjacent thereto when the memory cell is an end-row memory cell. The optimization component facilitates performing a Fowler-Nordheim channel erase to erase the subset of memory cells, and a predetermined voltage potential associated with an erase command is applied to each cell of the subset of memory cells to facilitate reducing fringing effect associated with the electromagnetic fields applied to the cells during the erase.

摘要翻译： 提供了一种存储器件，其包括便于擦除基本上均匀的电磁场中的存储器单元的优化部件，以及便于在基本均匀的电磁场中擦除存储器单元的方法。 优化组件有助于同时选择要擦除的存储器单元的子集，使得存储器单元子集中的存储单元具有与存储单元相邻的两个相邻存储器单元，其位于存储器的子集中，或者相邻的一个相邻存储器单元 当存储器单元是端行存储单元时。 优化组件有助于执行Fowler-Nordheim信道擦除来擦除存储器单元的子集，并且与擦除命令相关联的预定电压电位被施加到存储器单元子集的每个单元，以便于减少与电磁场相关联的边缘效应 在擦除期间应用于细胞。

公开(公告)号：US07746705B2

公开(公告)日：2010-06-29

申请号：US11953689

申请日：2007-12-10

申请人： Gulzar Ahmed Kathawala ,  Wei Zheng ,  Zhizheng Liu ,  Sung-Yong Chung ,  Timothy Thurgate ,  Kuo-Tung Chang ,  Sheung-Hee Park ,  Gabrielle Wing Han Leung

发明人： Gulzar Ahmed Kathawala ,  Wei Zheng ,  Zhizheng Liu ,  Sung-Yong Chung ,  Timothy Thurgate ,  Kuo-Tung Chang ,  Sheung-Hee Park ,  Gabrielle Wing Han Leung

IPC分类号： G11C16/04

CPC分类号： G11C16/3418

摘要： A memory device comprising an optimization component that facilitates erasing memory cells in a substantially homogeneous electromagnetic field and methods that facilitate erasing memory cells in a substantially homogeneous electromagnetic field are presented. The optimization component facilitates selecting a subset of memory cells to be erased at the same time, such that a memory cell in the subset of memory cells has two neighbor memory cells adjacent thereto that are in the subset of memory, or one neighbor memory cell adjacent thereto when the memory cell is an end-row memory cell. The optimization component facilitates performing a Fowler-Nordheim channel erase to erase the subset of memory cells, and a predetermined voltage potential associated with an erase command is applied to each cell of the subset of memory cells to facilitate reducing fringing effect associated with the electromagnetic fields applied to the cells during the erase.

摘要翻译： 提供了一种存储器件，其包括便于擦除基本上均匀的电磁场中的存储器单元的优化部件，以及便于在基本均匀的电磁场中擦除存储器单元的方法。 优化组件有助于同时选择要擦除的存储器单元的子集，使得存储器单元子集中的存储单元具有与存储单元相邻的两个相邻存储器单元，其位于存储器的子集中，或者相邻的一个相邻存储器单元 当存储器单元是端行存储单元时。 优化组件有助于执行Fowler-Nordheim信道擦除来擦除存储器单元的子集，并且与擦除命令相关联的预定电压电位被施加到存储器单元子集的每个单元，以便于减少与电磁场相关联的边缘效应 在擦除期间应用于细胞。

公开(公告)号：US20100208527A1

公开(公告)日：2010-08-19

申请号：US12773232

申请日：2010-05-04

申请人： Gulzar Ahmed Kathawala ,  Wei Zheng ,  Zhizheng Liu ,  Sung-Yong Chung ,  Timothy Thurgate ,  Kuo-Tung Chang ,  Sheung-Hee Park ,  Gabrielle Wing Han Leung

发明人： Gulzar Ahmed Kathawala ,  Wei Zheng ,  Zhizheng Liu ,  Sung-Yong Chung ,  Timothy Thurgate ,  Kuo-Tung Chang ,  Sheung-Hee Park ,  Gabrielle Wing Han Leung

IPC分类号： G11C16/04

CPC分类号： G11C16/3418

摘要： A memory device comprising an optimization component that facilitates erasing memory cells in a substantially homogeneous electromagnetic field and methods that facilitate erasing memory cells in a substantially homogeneous electromagnetic field are presented. The optimization component facilitates selecting a subset of memory cells to be erased at the same time, such that a memory cell in the subset of memory cells has two neighbor memory cells adjacent thereto that are in the subset of memory, or one neighbor memory cell adjacent thereto when the memory cell is an end-row memory cell. The optimization component facilitates performing a Fowler-Nordheim channel erase to erase the subset of memory cells, and a predetermined voltage potential associated with an erase command is applied to each cell of the subset of memory cells to facilitate reducing fringing effect associated with the electromagnetic fields applied to the cells during the erase.

摘要翻译： 提供了一种存储器件，其包括便于擦除基本上均匀的电磁场中的存储器单元的优化部件，以及便于在基本均匀的电磁场中擦除存储器单元的方法。 优化组件有助于同时选择要擦除的存储器单元的子集，使得存储器单元子集中的存储单元具有与存储单元相邻的两个相邻存储器单元，其位于存储器的子集中，或者相邻的一个相邻存储器单元 当存储器单元是端行存储单元时。 优化组件有助于执行Fowler-Nordheim信道擦除来擦除存储器单元的子集，并且与擦除命令相关联的预定电压电位被施加到存储器单元子集的每个单元，以便于减少与电磁场相关联的边缘效应 在擦除期间应用于细胞。

公开(公告)号：US20090147589A1

公开(公告)日：2009-06-11

申请号：US11953689

申请日：2007-12-10

申请人： Gulzar Ahmed Kathawala ,  Wei Zheng ,  Zhizheng Liu ,  Sung-Yong Chung ,  Timothy Thurgate ,  Kuo-Tung Chang ,  Sheung-Hee Park ,  Gabrielle Wing Han Leung

发明人： Gulzar Ahmed Kathawala ,  Wei Zheng ,  Zhizheng Liu ,  Sung-Yong Chung ,  Timothy Thurgate ,  Kuo-Tung Chang ,  Sheung-Hee Park ,  Gabrielle Wing Han Leung

IPC分类号： G11C16/18

CPC分类号： G11C16/3418

摘要： A memory device comprising an optimization component that facilitates erasing memory cells in a substantially homogeneous electromagnetic field and methods that facilitate erasing memory cells in a substantially homogeneous electromagnetic field are presented. The optimization component facilitates selecting a subset of memory cells to be erased at the same time, such that a memory cell in the subset of memory cells has two neighbor memory cells adjacent thereto that are in the subset of memory, or one neighbor memory cell adjacent thereto when the memory cell is an end-row memory cell. The optimization component facilitates performing a Fowler-Nordheim channel erase to erase the subset of memory cells, and a predetermined voltage potential associated with an erase command is applied to each cell of the subset of memory cells to facilitate reducing fringing effect associated with the electromagnetic fields applied to the cells during the erase.

摘要翻译： 提供了一种存储器件，其包括便于擦除基本上均匀的电磁场中的存储器单元的优化部件，以及便于在基本均匀的电磁场中擦除存储器单元的方法。 优化组件有助于同时选择要擦除的存储器单元的子集，使得存储器单元子集中的存储单元具有与存储单元相邻的两个相邻存储器单元，其位于存储器的子集中，或者相邻的一个相邻存储器单元 当存储器单元是端行存储单元时。 优化组件有助于执行Fowler-Nordheim信道擦除来擦除存储器单元的子集，并且与擦除命令相关联的预定电压电位被施加到存储器单元子集的每个单元，以便于减少与电磁场相关联的边缘效应 在擦除期间应用于细胞。

公开(公告)号：US07995386B2

公开(公告)日：2011-08-09

申请号：US12275663

申请日：2008-11-21

申请人： Yuji Mizuguchi ,  Mark W. Randolph ,  Darlene Gay Hamilton ,  Yi He ,  Zhizheng Liu ,  Yanxia (Emma) Lin ,  Xianmin Yi ,  Gulzar Kathawala ,  Amol Ramesh Joshi ,  Kuo-Tung Chang ,  Edward Franklin Runnion ,  Sung-Chul Lee ,  Sung-Yong Chung ,  Yanxiang Liu ,  Yu Sun

发明人： Yuji Mizuguchi ,  Mark W. Randolph ,  Darlene Gay Hamilton ,  Yi He ,  Zhizheng Liu ,  Yanxia (Emma) Lin ,  Xianmin Yi ,  Gulzar Kathawala ,  Amol Ramesh Joshi ,  Kuo-Tung Chang ,  Edward Franklin Runnion ,  Sung-Chul Lee ,  Sung-Yong Chung ,  Yanxiang Liu ,  Yu Sun

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G11C16/08 ,  G11C16/3427

摘要： Systems, methods, and devices that facilitate applying a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected during a read or verify operation to facilitate reducing adjacent wordline disturb are presented. A memory component can comprise an optimized operation component that can apply a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected for a read or verify operation, based at least in part on predefined operation criteria, to facilitate reducing adjacent wordline disturb in the selected memory cell to facilitate reducing a shift in the voltage threshold and maintain a desired operation window. The optimized operation component optionally can include an evaluator component that can facilitate determining whether a negative gate voltage applied to adjacent wordlines is to be adjusted to facilitate reducing adjacent wordline disturb below a predetermined threshold amount.

摘要翻译： 提出了有助于将预定义的负栅极电压施加到与在读取或验证操作期间选择的存储器单元相关联的所选字线相邻的字线的系统，方法和设备，以便于减少相邻字线干扰。 存储器组件可以包括优化的操作部件，其可以至少部分地基于预定义的操作标准，将预定义的负栅极电压施加到与被选择用于读取或验证操作所选择的存储器单元相关联的所选字线相邻的字线上，以便减少 所选择的存储单元中的相邻字线干扰，以便减少电压阈值的移位并保持期望的操作窗口。 优化的操作组件可选地可以包括评估器组件，其可以便于确定施加到相邻字线的负栅极电压是否被调整以便于将相邻字线干扰降低到低于预定阈值量。

公开(公告)号：US20100128521A1

公开(公告)日：2010-05-27

申请号：US12275663

申请日：2008-11-21

申请人： Yuji Mizuguchi ,  Mark W. Randolph ,  Darlene Gay Hamilton ,  Yi He ,  Zhizheng Liu ,  Yanxia (Emma) Lin ,  Xianmin Yi ,  Gulzar Kathawala ,  Amol Ramesh Joshi ,  Kuo-Tung Chang ,  Edward Franklin Runnion ,  Sung-Chul Lee ,  Sung-Yong Chung ,  Yanxiang Liu ,  Yu Sun

发明人： Yuji Mizuguchi ,  Mark W. Randolph ,  Darlene Gay Hamilton ,  Yi He ,  Zhizheng Liu ,  Yanxia (Emma) Lin ,  Xianmin Yi ,  Gulzar Kathawala ,  Amol Ramesh Joshi ,  Kuo-Tung Chang ,  Edward Franklin Runnion ,  Sung-Chul Lee ,  Sung-Yong Chung ,  Yanxiang Liu ,  Yu Sun

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G11C16/08 ,  G11C16/3427

摘要： Systems, methods, and devices that facilitate applying a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected during a read or verify operation to facilitate reducing adjacent wordline disturb are presented. A memory component can comprise an optimized operation component that can apply a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected for a read or verify operation, based at least in part on predefined operation criteria, to facilitate reducing adjacent wordline disturb in the selected memory cell to facilitate reducing a shift in the voltage threshold and maintain a desired operation window. The optimized operation component optionally can include an evaluator component that can facilitate determining whether a negative gate voltage applied to adjacent wordlines is to be adjusted to facilitate reducing adjacent wordline disturb below a predetermined threshold amount.

摘要翻译： 提出了有助于将预定义的负栅极电压施加到与在读取或验证操作期间选择的存储器单元相关联的所选字线相邻的字线的系统，方法和设备，以便于减少相邻字线干扰。 存储器组件可以包括优化的操作部件，其可以至少部分地基于预定义的操作标准，将预定义的负栅极电压施加到与被选择用于读取或验证操作所选择的存储器单元相关联的所选字线相邻的字线上，以便减少 所选择的存储单元中的相邻字线干扰，以便减少电压阈值的移位并保持期望的操作窗口。 优化的操作组件可选地可以包括评估器组件，其可以便于确定施加到相邻字线的负栅极电压是否被调整以便于将相邻字线干扰降低到低于预定阈值量。

公开(公告)号：US07029975B1

公开(公告)日：2006-04-18

申请号：US10839561

申请日：2004-05-04

申请人： Shenqing Fang ,  Kuo-Tung Chang ,  Pavel Fastenko ,  Kazuhiro Mizutani

发明人： Shenqing Fang ,  Kuo-Tung Chang ,  Pavel Fastenko ,  Kazuhiro Mizutani

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/513

摘要： A method and apparatus for coupling to a source line is disclosed. A semiconductor structure having an array of memory cells arranged in rows and columns is described. The array of memory cells includes a source region that is implanted with n-type dopants isolated between an adjoining pair of the non-intersecting STI regions and isolated from a drain region during the implantation. A source contact is located along a row of drain contacts that are coupled to drain regions of a row of memory cells and the source contact is coupled to the source region for providing electrical coupling with a plurality of source lines. The isolating of the implanted source region from the drain region during the implanting enables coupling of the source contact to the source lines while maintaining the n-type dopants between the STI regions and avoiding lateral diffusion to a bit-line.

摘要翻译： 公开了一种用于耦合到源极线的方法和装置。 描述了具有排列成行和列的存储单元阵列的半导体结构。 存储单元阵列包括源区域，其注入在相邻的一对不相交的STI区域之间隔离并在植入期间与漏区隔离的n型掺杂剂。 源极触点沿着一排漏极触点排列，其被连接到一行存储器单元的漏极区域，并且源极触点耦合到源极区域以提供与多个源极线的电耦合。 在植入期间将注入的源极区域与漏极区域隔离使得能够将源极接触耦合到源极线，同时保持STI区域之间的n型掺杂剂并且避免横向扩散到位线。

公开(公告)号：US07301193B2

公开(公告)日：2007-11-27

申请号：US10762445

申请日：2004-01-22

申请人： Shenqing Fang ,  Timothy Thurgate ,  Kuo-Tung Chang ,  Richard Fastow ,  Angela T. Hui ,  Kazuhiro Mizutani ,  Kelwin Ko ,  Hiroyuki Kinoshita ,  Yu Sun ,  Hiroyuki Ogawa

发明人： Shenqing Fang ,  Timothy Thurgate ,  Kuo-Tung Chang ,  Richard Fastow ,  Angela T. Hui ,  Kazuhiro Mizutani ,  Kelwin Ko ,  Hiroyuki Kinoshita ,  Yu Sun ,  Hiroyuki Ogawa

IPC分类号： H01L29/788

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L21/743 ,  H01L29/41766 ,  H01L29/66636

摘要： According to one exemplary embodiment, a floating gate memory cell comprises a stacked gate structure situated on a substrate and situated over a channel region in the substrate. The floating gate memory cell further comprises a recess formed in the substrate adjacent to the stacked gate structure, where the recess has a sidewall, a bottom, and a depth. According to this exemplary embodiment, the floating gate memory cell further comprises a source situated adjacent to the sidewall of the recess and under the stacked gate structure. The floating gate memory cell further comprises a Vss connection region situated under the bottom of the recess and under the source, where the Vss connection region is connected to the source. The Vss connection region being situated under the bottom of the recess causes the source to have a reduced lateral diffusion in the channel region.

摘要翻译： 根据一个示例性实施例，浮动栅极存储器单元包括位于衬底上并位于衬底中的沟道区域上方的堆叠栅极结构。 浮动栅极存储单元还包括形成在衬底中的与堆叠的栅极结构相邻的凹部，其中凹部具有侧壁，底部和深度。 根据该示例性实施例，浮动栅极存储单元还包括位于与凹部的侧壁相邻并位于堆叠栅极结构下方的源极。 浮动栅极存储单元还包括位于凹部底部下方和源极之下的Vss连接区域，其中Vss连接区域连接到源极。 位于凹部底部下方的Vss连接区使得源在通道区域中具有减小的横向扩散。

公开(公告)号：US07151028B1

公开(公告)日：2006-12-19

申请号：US10981174

申请日：2004-11-04

申请人： Shenqing Fang ,  Rinji Sugino ,  Kuo-Tung Chang ,  Zhigang Wang ,  Kazuhiro Mizutani ,  Pavel Fastenko

发明人： Shenqing Fang ,  Rinji Sugino ,  Kuo-Tung Chang ,  Zhigang Wang ,  Kazuhiro Mizutani ,  Pavel Fastenko

IPC分类号： H01L21/26

CPC分类号： H01L29/66636 ,  H01L29/1037 ,  H01L29/66659 ,  H01L29/66825 ,  H01L29/7881

摘要： According to one exemplary embodiment, a method for fabricating a floating gate memory cell on a substrate comprises a step of forming a first spacer adjacent to a source sidewall of a stacked gate structure, where the stacked gate structure is situated over a channel region in the substrate. The method further comprises forming a high energy implant doped region adjacent to the first spacer in a source region of the substrate. The method further comprises forming a recess in the source region, where a sidewall of the recess is situated adjacent to a source of the floating gate memory cell, and where forming the recess comprises removing the first spacer. The method further comprises forming a second spacer adjacent to the source sidewall of the stacked gate structure, where the second spacer extends to a bottom of the recess, and where the second spacer comprises plasma-grown oxide.

摘要翻译： 根据一个示例性实施例，用于在衬底上制造浮动栅极存储器单元的方法包括形成邻近层叠栅极结构的源极侧壁的第一间隔物的步骤，其中堆叠的栅极结构位于 基质。 该方法还包括在衬底的源区中形成与第一间隔物相邻的高能注入掺杂区。 该方法还包括在源极区域中形成凹部，其中凹部的侧壁位于与浮动栅极存储单元的源极相邻处，并且其中形成凹槽包括移除第一间隔物。 该方法还包括形成邻近层叠栅极结构的源极侧壁的第二间隔物，其中第二间隔物延伸到凹部的底部，并且其中第二间隔物包括等离子体生长的氧化物。