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    MOSFET having a low aspect ratio between the gate and the source/drain
    4.
    发明授权
    MOSFET having a low aspect ratio between the gate and the source/drain 失效
    MOSFET在栅极和源极/漏极之间具有低的纵横比

    公开(公告)号：US06528855B2

    公开(公告)日：2003-03-04

    申请号：US09911894

    申请日：2001-07-24

    申请人： Qiuyi Ye ,  William Tonti ,  Yujun Li ,  Jack A. Mandelman

    发明人： Qiuyi Ye ,  William Tonti ,  Yujun Li ,  Jack A. Mandelman

    IPC分类号： H01L29772

    CPC分类号： H01L29/0653 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/7834

    摘要： A MOSFET having a new source/drain (S/D) structure is particularly adapted to smaller feature sizes of modern CMOS technology. The S/D conductors are located on the shallow trench isolation (STI) to achieve low junction leakage and low junction capacitance. The S/D junction depth is defined by an STI etch step (according to a first method of making the MOSFET) or a silicon etch step (according to a second method of making the MOSFET). By controlling the etch depth, a very shallow junction depth is achieved. There is a low variation of gate length, since the gate area is defined by etching crystal silicon, not by etching polycrystalline silicon. There is a low aspect ratio between the gate and the S/D, since the gate conductor and the source and drain conductors are aligned on same level. A suicide technique is applied to the source and drain for low parasitic resistance; however, this will not result in severe S/D junction leakage, since the source and drain conductors sit on the STI.

    摘要翻译： 具有新的源极/漏极（S / D）结构的MOSFET特别适用于现代CMOS技术的较小特征尺寸。 S / D导体位于浅沟槽隔离（STI）上，以实现低结漏电和低结电容。 通过STI蚀刻步骤（根据制造MOSFET的第一种方法）或硅蚀刻步骤（根据制造MOSFET的第二种方法）限定S / D结深度。 通过控制蚀刻深度，实现非常浅的结深度。 栅极长度的变化很小，因为栅极区域是通过蚀刻晶体硅来定义的，而不是蚀刻多晶硅。 由于栅极导体和源极和漏极导体在同一个电平上对齐，栅极和S / D之间的纵横比较低。 自杀技术应用于源极和漏极，用于低寄生电阻; 然而，这不会导致严重的S / D结泄漏，因为源极和漏极导体位于STI上。

    Device fabrication by anisotropic wet etch
    7.
    发明授权
    Device fabrication by anisotropic wet etch 失效
    通过各向异性湿法蚀刻的器件制造

    公开(公告)号：US07696539B2

    公开(公告)日：2010-04-13

    申请号：US12141878

    申请日：2008-06-18

    申请人： Yujun Li ,  Kenneth T. Settlemyer, Jr. ,  Jochen Beintner

    发明人： Yujun Li ,  Kenneth T. Settlemyer, Jr. ,  Jochen Beintner

    IPC分类号： H01L29/80

    CPC分类号： H01L21/84 ,  H01L21/30608 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/66772 ,  H01L29/66818 ,  H01L29/785

    摘要： A method of fabrication and a field effect device structure are presented that reduce source/drain capacitance and allow for device body contact. A Si based material pedestal is produced, the top surface and the sidewalls of which are oriented in a way to be substantially parallel with selected crystallographic planes of the pedestal and of a supporting member. The pedestal is wet etched with an anisotropic solution containing ammonium hydroxide. The sidewalls of the pedestal become faceted forming a segment in the pedestal with a reduced cross section. The dopant concentration in the reduced cross section segment is chosen to be sufficiently high for it to provide for electrical continuity through the pedestal.

    摘要翻译： 提出了一种制造方法和场效应器件结构，其减少源/漏电容并允许器件接触。 产生基于Si的材料基座，其顶表面和其侧壁的方向定位成与基座和支撑构件的选定结晶平面基本平行。 用包含氢氧化铵的各向异性溶液湿式蚀刻基座。 基座的侧壁变小，在基座上形成截面减小的部分。 选择减小的横截面段中的掺杂剂浓度足够高以使其提供穿过基座的电连续性。

    Process for fabrication of FinFETs
    8.
    发明授权
    Process for fabrication of FinFETs 有权
    FinFET的制造工艺

    公开(公告)号：US07470570B2

    公开(公告)日：2008-12-30

    申请号：US11559460

    申请日：2006-11-14

    申请人： Jochen Beintner ,  Gary B. Bronner ,  Ramachandra Divakaruni ,  Yujun Li

    发明人： Jochen Beintner ,  Gary B. Bronner ,  Ramachandra Divakaruni ,  Yujun Li

    IPC分类号： H01L21/00

    CPC分类号： H01L29/7851 ,  H01L29/66795

    摘要： A method of fabricating a plurality of FinFETs on a semiconductor substrate in which the gate width of each individual FinFET is defined utilizing only a single etching process, instead of two or more, is provided. The inventive method results in improved gate width control and less variation of the gate width of each individual gate across the entire surface of the substrate. The inventive method achieves the above by utilizing a modified sidewall image transfer (SIT) process in which an insulating spacer that is later replaced by a gate conductor is employed and a high-density bottom up oxide fill is used to isolate the gate from the substrate.

    摘要翻译： 提供了在半导体衬底上制造多个FinFET的方法，其中仅使用单个蚀刻工艺限定每个单个FinFET的栅极宽度，而不是两个或更多个。 本发明的方法导致改善的栅极宽度控制和在基板的整个表面上每个单独栅极的栅极宽度的变化较小。 本发明的方法通过利用改进的侧壁图像转印（SIT）工艺实现上述，其中采用稍后被栅极导体替代的绝缘间隔物，并且使用高密度底部向上氧化物填充物将栅极与衬底隔离 。

    PROCESS FOR FABRICATION OF FINFETs
    9.
    发明申请
    PROCESS FOR FABRICATION OF FINFETs 有权
    FINFET制造工艺

    公开(公告)号：US20080111184A1

    公开(公告)日：2008-05-15

    申请号：US11559460

    申请日：2006-11-14

    申请人： Jochen Beintner ,  Gary B. Bronner ,  Ramachandra Divakaruni ,  Yujun Li

    发明人： Jochen Beintner ,  Gary B. Bronner ,  Ramachandra Divakaruni ,  Yujun Li

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7851 ,  H01L29/66795

    摘要： A method of fabricating a plurality of FinFETs on a semiconductor substrate in which the gate width of each individual FinFET is defined utilizing only a single etching process, instead of two or more, is provided. The inventive method results in improved gate width control and less variation of the gate width of each individual gate across the entire surface of the substrate. The inventive method achieves the above by utilizing a modified sidewall image transfer (SIT) process in which an insulating spacer that is later replaced by a gate conductor is employed and a high-density bottom up oxide fill is used to isolate the gate from the substrate.

    摘要翻译： 提供了在半导体衬底上制造多个FinFET的方法，其中仅使用单个蚀刻工艺限定每个单个FinFET的栅极宽度，而不是两个或更多个。 本发明的方法导致改善的栅极宽度控制和在基板的整个表面上每个单独栅极的栅极宽度的变化较小。 本发明的方法通过利用改进的侧壁图像转印（SIT）工艺实现上述，其中采用稍后被栅极导体替代的绝缘间隔物，并且使用高密度底部向上氧化物填充物将栅极与衬底隔离 。

    Structure and method of forming a notched gate field effect transistor
    10.
    发明授权
    Structure and method of forming a notched gate field effect transistor 失效
    形成陷波栅场效应晶体管的结构和方法

    公开(公告)号：US06905976B2

    公开(公告)日：2005-06-14

    申请号：US10249771

    申请日：2003-05-06

    申请人： Jochen Beintner ,  Yujun Li ,  Naim Moumen ,  Porshia Shane Wrschka

    发明人： Jochen Beintner ,  Yujun Li ,  Naim Moumen ,  Porshia Shane Wrschka

    IPC分类号： H01L29/423 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L21/302

    CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L21/28044 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/49 ,  H01L29/665 ,  Y10S438/933

    摘要： The structure and method of forming a notched gate MOSFET disclosed herein addresses such problems as device reliability. A gate dielectric (e.g. gate oxide) is formed on the surface of an active area on the semiconductor substrate, preferably defined by an isolation trench region. A layer of polysilicon is then deposited on the gate dielectric. This step is followed by depositing a layer of silicon germanium) (SiGe). The sidewalls of the polysilicon layer are then laterally etched, selective to the SiGe layer to create a notched gate conductor structure, with the SiGe layer being broader than the underlying polysilicon layer. Sidewall spacers are preferably formed on sidewalls of the SiGe layer and the polysilicon layer. A silicide layer is preferably formed as a self-aligned silicide from a polysilicon layer deposited over the SiGe layer, to reduce resistance of the gate conductor. One or more other processing steps (e.g. source and drain implants, extension implants, and pocket lightly doped drain (LDD) implants), gate conductor stack doping, and silicidation are preferably performed in completing the transistor.

    摘要翻译： 本文公开的形成缺口栅极MOSFET的结构和方法解决了诸如器件可靠性的问题。 栅电介质（例如栅极氧化物）形成在半导体衬底上的有源区的表面上，优选由隔离沟槽区限定。 然后在栅极电介质上沉积多晶硅层。 该步骤之后是沉积一层硅锗）（SiGe）。 然后横向蚀刻多晶硅层的侧壁，对SiGe层有选择性，以产生刻蚀的栅极导体结构，其中SiGe层比下面的多晶硅层宽。 侧壁间隔物优选形成在SiGe层和多晶硅层的侧壁上。 硅化物层优选从沉积在SiGe层上的多晶硅层形成为自对准硅化物，以降低栅极导体的电阻。 优选在完成晶体管时执行一个或多个其它处理步骤（例如源极和漏极注入，延伸注入和袖带轻掺杂漏极（LDD）注入），栅极导体堆叠掺杂和硅化。