公开(公告)号：US06489835B1

公开(公告)日：2002-12-03

申请号：US09941454

申请日：2001-08-28

Applicant: Quan Yu ,  Edwin Chan

Inventor： Quan Yu ,  Edwin Chan

IPC: G05F110

CPC classification number: G05F3/30 ,  G05F3/267

Abstract: A bandgap reference circuit that operates with a voltage supply that can be lass than 1 volt and that has one stable, non-zero current operating point. The core has a current generator embedded within it and includes one operational amplifier that provides a self-regulated voltage for several transistors used in the circuit

Abstract translation: 带隙参考电路，其工作电压可低于1伏，具有一个稳定的非零电流工作点。 内核具有嵌入其中的电流发生器，并且包括一个运算放大器，为电路中使用的多个晶体管提供自调节电压

公开(公告)号：US06710641B1

公开(公告)日：2004-03-23

申请号：US10308420

申请日：2002-12-02

Applicant: Quan Yu ,  Edwin Chan

Inventor： Quan Yu ,  Edwin Chan

IPC: G05F110

CPC classification number: G05F3/30 ,  G05F3/267

Abstract: A bandgap reference circuit that operates with a voltage supply that can be less than 1 volt and that has one stable, non-zero current operating point. The core has a current generator embedded within it and includes one operational amplifier that provides a self-regulated voltage for several transistors used in the circuit.

Abstract translation: 带隙参考电路，其工作电压可以小于1伏，并具有一个稳定的非零电流工作点。 内核具有嵌入其中的电流发生器，并且包括一个运算放大器，为电路中使用的多个晶体管提供自调节电压。

公开(公告)号：US20080024172A1

公开(公告)日：2008-01-31

申请号：US11460122

申请日：2006-07-26

Applicant: Quan Yu ,  Ming Qu

Inventor： Quan Yu ,  Ming Qu

IPC: H03K19/094

CPC classification number: H03K19/01707 ,  H03F1/483 ,  H03F3/45183 ,  H03F2200/36 ,  H03F2203/45248 ,  H03F2203/45318 ,  H03F2203/45352 ,  H03F2203/45374 ,  H03F2203/45638 ,  H03F2203/45702 ,  H03K19/018514

Abstract: An actively compensated CML circuit includes a CML buffer circuit and a bandwidth expansion circuit. The CML buffer circuit includes a first MOS transistor and a second MOS transistor in a differential pair configuration. A first load resistor is coupled to a first MOS transistor drain at a first output terminal and a second load resistor is coupled to a second MOS transistor drain at a second output terminal. The bandwidth expansion circuit is coupled to the CML buffer circuit in a source follower configuration. The bandwidth expansion circuit includes a third MOS transistor and a fourth MOS transistor. A capacitor is coupled across a third MOS transistor source and a fourth MOS transistor source. The fourth MOS transistor and the third MOS transistor generate a high pass function at the first output terminal and the second output terminal.

Abstract translation: 积极补偿的CML电路包括CML缓冲电路和带宽扩展电路。 CML缓冲电路包括第一MOS晶体管和差分对配置中的第二MOS晶体管。 第一负载电阻器在第一输出端耦合到第一MOS晶体管漏极，第二负载电阻器在第二输出端子耦合到第二MOS晶体管漏极。 带宽扩展电路以源跟随器配置耦合到CML缓冲电路。 带宽扩展电路包括第三MOS晶体管和第四MOS晶体管。 电容器耦合在第三MOS晶体管源极和第四MOS晶体管源极之间。 第四MOS晶体管和第三MOS晶体管在第一输出端和第二输出端产生高通功能。

公开(公告)号：US20140003480A1

公开(公告)日：2014-01-02

申请号：US13538930

申请日：2012-06-29

Applicant: Ming Qu ,  Yuanping Chen ,  Yuntao Zhu ,  Quan Yu ,  Kochung Lee

Inventor： Ming Qu ,  Yuanping Chen ,  Yuntao Zhu ,  Quan Yu ,  Kochung Lee

IPC: H04B17/00

CPC classification number: H03L7/087 ,  G01R29/26 ,  H03L7/0807 ,  H03L7/081 ,  H03L7/0998 ,  H04B17/104 ,  H04L1/205 ,  H04L1/243 ,  H04L7/033

Abstract: A system and method are disclosed for performing on die jitter tolerance testing. A set of clocks are generated based on an input signal. The set of clocks include in an in-phase signal based on the data switching edge of the input signal. Additionally, the set of clocks include an inverted clock phase shifted by 180 degrees, and a pair of clocks phase shifted positively and negatively by a certain number of degrees, θ. Data input is sampled based on the inverted clock and the two phase shifted clocks. The eye opening of the input signal can be determined based on whether each of the inverted clock and the two phase shifted clocks sample the correct data from the input signal at various θ values.

Abstract translation: 公开了一种用于执行裸片抖动容限测试的系统和方法。 基于输入信号产生一组时钟。 该组时钟包括基于输入信号的数据切换沿的同相信号。 此外，该组时钟包括偏移180度的反相时钟相位和一对相位偏移一定数量度θ的时钟。 基于反相时钟和两个相移时钟对数据输入进行采样。 可以基于反相时钟和两个相移时钟中的每一个是否以各种θ值从输入信号中采样正确的数据来确定输入信号的开眼。

公开(公告)号：US07697570B2

公开(公告)日：2010-04-13

申请号：US10476407

申请日：2002-04-29

Applicant: Zhenya Li ,  Guzheng Wu ,  Quan Yu ,  Shoubo Xie ,  Konggang Wei

Inventor： Zhenya Li ,  Guzheng Wu ,  Quan Yu ,  Shoubo Xie ,  Konggang Wei

IPC: H04J3/00

CPC classification number: H04Q11/04 ,  H04Q2213/13166 ,  H04Q2213/13214 ,  H04Q2213/13292 ,  H04Q2213/1336

Abstract: A method for multi-path TDM data transmission includes: applying a plurality of high-speed serial lines to connect a center switch network board to a plurality of service boards; multiplexing multi-path TDM data from the center switch network board at transmitting side, and transmitting TDM data multiplexed in batch via one of the high-speed serial lines to one of the service boards; at receiving side, serial receiving the TDM data multiplexed and de-multiplexing the TDM data multiplexed to multiple TDM paths. The TDM bridge connector includes: a TDM high-speed serial transmitting adaptive circuit, and a TDM high-speed serial receiving adaptive circuit and a clock control circuit. The invention increases greatly transmission capacity and looses the requirement of clock synchronization, so the system reliability is greatly raised.

Abstract translation: 一种用于多径TDM数据传输的方法包括：应用多条高速串行线路将中央交换网络板连接到多个业务板; 从发送侧的中心交换网络多路复用多路TDM数据，并通过一条高速串行线路批量发送TDM数据到其中一个业务板; 在接收侧，串行接收多路复用TDM多路复用TDM多路复用TDM数据的TDM数据并将其解复用。 TDM桥​​接器包括TDM高速串行传输自适应电路和TDM高速串行接收自适应电路和时钟控制电路。 本发明大大提高了传输容量，不再需要时钟同步，因此系统可靠性大大提高。

公开(公告)号：US07382153B2

公开(公告)日：2008-06-03

申请号：US11459880

申请日：2006-07-25

Applicant: Quing Ou-yang ,  Quan Yu ,  Ming Qu

Inventor： Quing Ou-yang ,  Quan Yu ,  Ming Qu

IPC: H03K17/16

CPC classification number: H03K19/0005

Abstract: A circuit for calibrating a resistance value on an integrated circuit includes a resistor network, a reference voltage generator, a comparator, a servo loop, and a shift register. The resistor network includes a plurality of resistor and switch pairs in parallel. The resistor network further includes a servo resistor in series with a servo resistor switch such that the servo resistor and servo resistor switch are in parallel with the plurality of resistor and switch pairs. The servo loop generates a shift register gating signal and includes a current sample register for storing a current comparator output data value and a previous sample register for storing a previous comparator output data value. The shift register, upon receipt of a shift register gating signal at a first state, inputs the current comparator output data value to shift data bits through the shift register.

Abstract translation: 用于校准集成电路上的电阻值的电路包括电阻网络，参考电压发生器，比较器，伺服环路和移位寄存器。 电阻网络包括并联的多个电阻器和开关对。 电阻网络还包括与伺服电阻器开关串联的伺服电阻器，使得伺服电阻器和伺服电阻器开关与多个电阻器和开关对并联。 伺服环路产生移位寄存器门控信号，并包括用于存储当前比较器输出数据值的当前采样寄存器和用于存储先前比较器输出数据值的先前采样寄存器。 移位寄存器在第一状态下接收到移位寄存器选通信号时，输入当前比较器输出数据值以通过移位寄存器移位数据位。

公开(公告)号：US20080061837A1

公开(公告)日：2008-03-13

申请号：US11467528

申请日：2006-08-25

Applicant: Feng Xu ,  Quan Yu ,  Ming Qu

Inventor： Feng Xu ,  Quan Yu ,  Ming Qu

IPC: H03K19/086

CPC classification number: H03K19/018528

Abstract: A current mode logic circuit includes a current mode logic driver circuit and a transistor biasing improvement circuit. The transistor biasing improvement circuit includes a first current source coupled to a first output node of the current mode logic driver circuit and a second current source coupled to a second output node of the current mode logic driver circuit. The first current source and the second current source raise a common mode voltage at the first output node and the second output node.

Abstract translation: 电流模式逻辑电路包括电流模式逻辑驱动器电路和晶体管偏置改善电路。 晶体管偏置改善电路包括耦合到电流模式逻辑驱动器电路的第一输出节点的第一电流源和耦合到当前模式逻辑驱动器电路的第二输出节点的第二电流源。 第一电流源和第二电流源在第一输出节点和第二输出节点处提高共模电压。

公开(公告)号：US08610479B2

公开(公告)日：2013-12-17

申请号：US13276269

申请日：2011-10-18

Applicant: Kochung Lee ,  Quan Yu ,  Yuntao Zhu ,  Lei Xie ,  Ming Qu

Inventor： Kochung Lee ,  Quan Yu ,  Yuntao Zhu ,  Lei Xie ,  Ming Qu

IPC: G06F1/04

CPC classification number: H03L7/22

Abstract: A system and method are disclosed for generating a high accuracy and low power on die reference clock. An LC clock is generated on die and a frequency divider lowers the LC clock frequency to a target reference frequency. An RCO clock is generated on die with an unknown initial frequency. The RCO clock and target reference clock are compared to determine in which direction the frequency of the RCO clock should be adjusted to move closer to the target reference frequency. A signal is sent causing a current source or capacitor in the RCO circuit to be modified. Therefore, the RCO clock frequency is adjusted. The RCO circuit is repeatedly adjusted until the RCO clock frequency is sufficiently accurate. The LC clock is disabled to conserve the power that would have been consumed in generating the LC clock.

Abstract translation: 公开了一种用于在芯片参考时钟上产生高精度和低功耗的系统和方法。 在芯片上产生LC时钟，分频器将LC时钟频率降低到目标参考频率。 在未知的初始频率的芯片上产生RCO时钟。 比较RCO时钟和目标参考时钟，确定在哪个方向上调整RCO时钟的频率以更接近目标参考频率。 发送信号，导致RCO电路中的电流源或电容器被修改。 因此，调整RCO时钟频率。 RCO电路重复调整，直到RCO时钟频率足够准确。 LC时钟被禁用，以节省在生成LC时钟时消耗的功率。

公开(公告)号：US20130093466A1

公开(公告)日：2013-04-18

申请号：US13276269

申请日：2011-10-18

Applicant: Kochung Lee ,  Quan Yu ,  Yuntao Zhu ,  Lei Xie ,  Ming Qu

Inventor： Kochung Lee ,  Quan Yu ,  Yuntao Zhu ,  Lei Xie ,  Ming Qu

IPC: H03D13/00

CPC classification number: H03L7/22

Abstract: A system and method are disclosed for generating a high accuracy and low power on die reference clock. An LC clock is generated on die and a frequency divider lowers the LC clock frequency to a target reference frequency. An RCO clock is generated on die with an unknown initial frequency. The RCO clock and target reference clock are compared to determine in which direction the frequency of the RCO clock should be adjusted to move closer to the target reference frequency. A signal is sent causing a current source or capacitor in the RCO circuit to be modified. Therefore, the RCO clock frequency is adjusted. The RCO circuit is repeatedly adjusted until the RCO clock frequency is sufficiently accurate. The LC clock is disabled to conserve the power that would have been consumed in generating the LC clock.

Abstract translation: 公开了一种用于在芯片参考时钟上产生高精度和低功耗的系统和方法。 在芯片上产生LC时钟，分频器将LC时钟频率降低到目标参考频率。 在未知的初始频率的芯片上产生RCO时钟。 比较RCO时钟和目标参考时钟，确定在哪个方向上调整RCO时钟的频率以更接近目标参考频率。 发送信号，导致RCO电路中的电流源或电容器被修改。 因此，调整RCO时钟频率。 RCO电路重复调整，直到RCO时钟频率足够准确。 LC时钟被禁用，以节省在生成LC时钟时消耗的功率。

公开(公告)号：US08923375B2

公开(公告)日：2014-12-30

申请号：US13538930

申请日：2012-06-29

Applicant: Ming Qu ,  Yuanping Chen ,  Yuntao Zhu ,  Quan Yu ,  Kochung Lee

Inventor： Ming Qu ,  Yuanping Chen ,  Yuntao Zhu ,  Quan Yu ,  Kochung Lee

IPC: H04B17/00

CPC classification number: H03L7/087 ,  G01R29/26 ,  H03L7/0807 ,  H03L7/081 ,  H03L7/0998 ,  H04B17/104 ,  H04L1/205 ,  H04L1/243 ,  H04L7/033

Abstract: A system and method are disclosed for performing on die jitter tolerance testing. A set of clocks are generated based on an input signal. The set of clocks include in an in-phase signal based on the data switching edge of the input signal. Additionally, the set of clocks include an inverted clock phase shifted by 180 degrees, and a pair of clocks phase shifted positively and negatively by a certain number of degrees, θ. Data input is sampled based on the inverted clock and the two phase shifted clocks. The eye opening of the input signal can be determined based on whether each of the inverted clock and the two phase shifted clocks sample the correct data from the input signal at various θ values.

Abstract translation: 公开了一种用于执行裸片抖动容限测试的系统和方法。 基于输入信号产生一组时钟。 该组时钟包括基于输入信号的数据切换沿的同相信号。 此外，该组时钟包括一个偏移180度的反相时钟相位和一对相位正负偏移一定数量的时钟。 基于反相时钟和两个相移时钟对数据输入进行采样。 输入信号的开眼可以基于​​每个反相时钟和两个相移时钟从各种输入信号中的输入信号中得到正确的数据来确定; 价值观。