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16 条记录 (耗时 0.016 秒)

    Method and built-in self-test apparatus for testing an integrated circuit which capture failure information for a selected failure
    4.
    发明授权
    Method and built-in self-test apparatus for testing an integrated circuit which capture failure information for a selected failure 失效
    用于测试集成电路的方法和内置自检装置，其捕获所选故障的故障信息

    公开(公告)号：US5912901A

    公开(公告)日：1999-06-15

    申请号：US823446

    申请日：1997-03-24

    申请人： R. Dean Adams ,  Michael R. Ouellette ,  Ronald J. Prilik

    发明人： R. Dean Adams ,  Michael R. Ouellette ,  Ronald J. Prilik

    IPC分类号： G01R31/28 ,  G01R31/3185 ,  G01R31/319 ,  G06F11/22 ,  G11C29/12

    CPC分类号： G01R31/318555 ,  G01R31/2884 ,  G01R31/319

    摘要： A built-in self-test (BIST) apparatus and method for testing an integrated circuit are disclosed which enable capture of failure data for a selected failure. The BIST apparatus comprises a clock generator, which generates at least a first clock signal, and a built-in self-tester, which applies predetermined input data patterns to the integrated circuit in response to the first clock signal. In addition, the BIST apparatus includes a data comparator for comparing output data received from the integrated circuit with expected output data. The data comparator detects a failure within the integrated circuit when the output data received from the integrated circuit differs from the expected output data. The BIST apparatus further includes a clock controller that disables the first clock signal in response to the detection of a selected occurrence of a failure. By enabling testing of the integrated circuit to be halted upon the occurrence of a selected failure, failure analysis of the integrated circuit is enhanced.

    摘要翻译： 公开了一种用于测试集成电路的内置自检（BIST）装置和方法，其能够捕获所选故障的故障数据。 BIST装置包括产生至少第一时钟信号的时钟发生器和内置自测试器，其响应于第一时钟信号将预定的输入数据模式应用于集成电路。 此外，BIST装置包括用于将从集成电路接收的输出数据与预期输出数据进行比较的数据比较器。 当从集成电路接收的输出数据与预期输出数据不同时，数据比较器检测集成电路内的故障。 BIST装置还包括时钟控制器，其响应于所选择的故障发生的检测而禁用第一时钟信号。 通过在所选择的故障发生时能够对要停止的集成电路进行测试，增强了集成电路的故障分析。

    Method and apparatus for testing memory cells for data retention faults
    5.
    发明授权
    Method and apparatus for testing memory cells for data retention faults 有权
    用于测试存储器单元用于数据保留故障的方法和装置

    公开(公告)号：US06681350B2

    公开(公告)日：2004-01-20

    申请号：US09681602

    申请日：2001-05-05

    申请人： R. Dean Adams ,  Aneesha P. Deo ,  Kamran Zarrineh

    发明人： R. Dean Adams ,  Aneesha P. Deo ,  Kamran Zarrineh

    IPC分类号： G11C2900

    CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/08 ,  G11C29/50016

    摘要： A method for testing memory cells for data retention faults is disclosed. A first logical value is stored in a first cell, and a second logical value is stored in a second cell of a memory device. The second cell shares the same column with the first cell. The bitlines associated with the first and second cells are prevented from being precharged before the second cell can be read. After the second cell has been read repeatedly, the first cell is read, and the bitlines associated with the first and second cells are precharged. At this point, a data retention fault is determined to have occurred if the first cell does not contain the first logical value.

    摘要翻译： 公开了一种用于测试存储器单元用于数据保持故障的方法。 第一逻辑值存储在第一单元中，第二逻辑值存储在存储器件的第二单元中。 第二个单元格与第一个单元格共享相同的列。 在第二单元可被读取之前，防止与第一和第二单元相关联的位线被预充电。 在重复读取第二单元之后，读取第一单元，并且与第一单元和第二单元相关联的位线被预充电。 此时，如果第一小区不包含第一逻辑值，则确定数据保留故障已经发生。

    High speed greater than or equal to compare circuit
    6.
    发明授权
    High speed greater than or equal to compare circuit 失效
    高速比大于等于比较电路

    公开(公告)号：US5592142A

    公开(公告)日：1997-01-07

    申请号：US529255

    申请日：1995-09-15

    申请人： R. Dean Adams ,  Donald A. Evans ,  Roy C. Flaker

    发明人： R. Dean Adams ,  Donald A. Evans ,  Roy C. Flaker

    IPC分类号： G06F7/02

    CPC分类号： G06F7/026

    摘要： The high speed greater than or equal to compare circuit comprises an equal to compare circuit having M number of exclusive-OR gates input into a NOR gate, each exclusive-OR gate N of the M number of exclusive-OR gates receiving as inputs a Nth bit of a first digital number having M bits and a corresponding Nth bit of a second digital number having M bits, wherein 1

    摘要翻译： 高于或等于比较电路的高速包括等于具有输入到或非门的M个异或门的等效电路，M个异或门的每个异或门N作为输入接收第N个 具有M比特的第一数字号码和具有M比特的第二数字号码的相应第N比特，其中1

    Built-in self test system and method for two-dimensional memory redundancy allocation
    7.
    发明授权
    Built-in self test system and method for two-dimensional memory redundancy allocation 失效
    内置自检系统和二维内存冗余分配方法

    公开(公告)号：US06907554B2

    公开(公告)日：2005-06-14

    申请号：US10249817

    申请日：2003-05-09

    申请人： R. Dean Adams ,  Thomas J. Eckenrode ,  Steven L. Gregor ,  Gary S. Koch

    发明人： R. Dean Adams ,  Thomas J. Eckenrode ,  Steven L. Gregor ,  Gary S. Koch

    IPC分类号： G11C29/44 ,  G11C29/00

    CPC分类号： G11C29/4401 ,  G11C29/44 ,  G11C2029/0401

    摘要： A built-in self test system (124) and method for two-dimensional memory redundancy allocation. The built-in self test system is adapted to allocate two redundant columns (116) and one redundant row (120) to an embedded memory (104) as needed to repair single cell failures (SCFs) within the rows (108) and columns of the memory. The self-test system includes a left-priority encoder (136), a right-priority encoder (140), and a greater-than-two detector (144). The left-priority encoder encodes the location of the first SCF most proximate the most-significant bit of the corresponding word. The right-priority encoder encodes the location of the first SCF most proximate the least-significant bit of the corresponding word. The greater-than-two detector determines whether a word contains more than two SCFs. If the greater-than-two detector detects that a word contains more than two SCFs, the built-in self test system identifies the corresponding row as being a must-fix row, since the number of SCFs exceeds the number of redundant columns.

    摘要翻译： 内置自检系统（124）和二维内存冗余分配方法。 所述内置自检系统适于根据需要将两个冗余列（116）和一个冗余行（120）分配给嵌入式存储器（104），以修复行（108）和列（108）中的单个单元故障（SCF） 记忆。 自检系统包括左优先编码器（136），右优先编码器（140）和大于二检测器（144）。 左优先级编码器对最接近相应字最高有效位的第一SCF的位置进行编码。 右优先编码器编码最接近对应字的最低有效位的第一SCF的位置。 大于2的检测器确定一个单词是否包含两个以上的SCF。 如果大于2的检测器检测到一个字含有两个以上的SCF，则内置的自检系统将相应的行识别为必须修复的行，因为SCF的数量超过冗余列的数量。

    Programmable memory built-in self-test combining microcode and finite state machine self-test
    8.
    发明授权
    Programmable memory built-in self-test combining microcode and finite state machine self-test 失效
    可编程存储器内置自检组合微码和有限状态机自检

    公开(公告)号：US06651201B1

    公开(公告)日：2003-11-18

    申请号：US09626715

    申请日：2000-07-26

    申请人： R. Dean Adams ,  Thomas J. Eckenrode ,  Steven L. Gregor ,  Kamran Zarrineh

    发明人： R. Dean Adams ,  Thomas J. Eckenrode ,  Steven L. Gregor ,  Kamran Zarrineh

    IPC分类号： G01R3128

    CPC分类号： G01R31/3187 ,  G01R31/2891 ,  G11C29/16

    摘要： A finite state machine (FSM) is used to generate, in real time, potentially long sequences of signals which control generation of signals for application to a memory structure during a self-test procedure which is provided in hardware on the same chip with the memory structure. The FSM-based instruction generator requires much less area than is required for storage of a corresponding number of microcode instructions and allows the built-in self-test (BIST) controller to have a modular architecture permitting re-use of hardware designs for the BIST arrangement with consequent reduction of elimination of design costs of the BIST arrangement to accommodate new memory designs. The sequential nature of the operation of a finite state machine as it progresses through a desired sequence of states is particularly well-suited to controlling capture of signals where access to high. speed data transfer circuits cannot otherwise be accommodated.

    摘要翻译： 有限状态机（FSM）用于实时地产生潜在的长序列信号，该序列控制信号的产生，以便在与存储器相同的芯片上的硬件中提供的自检过程期间应用于存储器结构 结构体。 基于FSM的指令生成器需要比存储相应数量的微代码指令所需的面积少得多的内存自检（BIST）控制器具有模块化架构，允许重新使用硬件设计用于BIST 从而减少了BIST安排的设计成本的消除以适应新的存储器设计。 有限状态机在其进行期望的状态序列的操作的顺序性质特别适合于控制对高访问信号的捕获。 速度数据传输电路不能适应。

    Asynchronous control of memory self test
    10.
    发明授权
    Asynchronous control of memory self test 有权
    内存自检异步控制

    公开(公告)号：US07203873B1

    公开(公告)日：2007-04-10

    申请号：US10861247

    申请日：2004-06-04

    申请人： R. Dean Adams ,  Robert Abbott ,  Xiaoliang Bai ,  Dwayne M. Burek

    发明人： R. Dean Adams ,  Robert Abbott ,  Xiaoliang Bai ,  Dwayne M. Burek

    IPC分类号： G11C29/00

    CPC分类号： G11C29/14 ,  G11C29/1201 ,  G11C2029/0405

    摘要： A memory logic built-in self-test (“BIST”) includes slow speed controller-to-collar signals, while allowing collars to test memories at full speed. A controller is configured to include control features and address, data, read/write, output evaluation, and redundancy calculation values are configured within the collars. The controller is further configured to handle scheduling of the collars and diagnostics interfacing. In addition, the collars are configured to allow BIST testing to be run serially, in parallel, or in groups. Collars are also configured to send diagnostic results back to the controller based on the initialization of the respective collars, thus providing a central interface for the diagnostics results.

    摘要翻译： 内置自检（“BIST”）的存储器逻辑包括速度较慢的控制器到外壳信号，同时允许套环全速测试存储器。 控制器被配置为包括控制特征和地址，数据，读/写，输出评估和冗余计算值在套环内配置。 控制器还被配置为处理套环和诊断接口的调度。 此外，项圈配置为允许BIST测试串行，并行或分组运行。 衣领还被配置为基于相应衣领的初始化将诊断结果发送回控制器，从而为诊断结果提供中央接口。