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    LOW POWER SIGNALING INTERFACE
    2.
    发明申请
    LOW POWER SIGNALING INTERFACE 审中-公开

    公开(公告)号：US20200294557A1

    公开(公告)日：2020-09-17

    申请号：US16828591

    申请日：2020-03-24

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Carl W. Werner

    IPC: G11C7/04 ,  G06F1/12 ,  G11C7/22 ,  G11C29/02 ,  G11C29/50 ,  H03K5/15 ,  H01L39/22

    Abstract: In a chip-to-chip signaling system includes at least one signaling link coupled between first and second ICs, the first IC has an interface coupled to the signaling link and timed by a first interface timing signal. The second IC has an interface coupled to the signaling link and timed by a second interface timing signal that is mesochronous with respect to the first interface timing signal. The second IC further has phase adjustment circuitry that adjusts a phase of the second interface timing signal using a digital counter implemented with Josephson-junction circuit elements.

    Differential cryogenic transmitter
    3.
    发明授权
    Differential cryogenic transmitter 有权

    公开(公告)号：US10177749B2

    公开(公告)日：2019-01-08

    申请号：US15478757

    申请日：2017-04-04

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Carl W. Werner

    IPC: H03K5/22 ,  H04L25/02 ,  H03K3/38 ,  H03K19/0175 ,  H03K19/195

    Abstract: In an integrated-circuit component having a signal transmitter receives a transmitter power supply that cycles periodically between power-off and power-on voltage levels to define a sequence of enable intervals during which the signal transmitter is to output voltage levels corresponding to respective transmit data bits onto an external signaling link. The signal transmitter generates, at the start of each output-enable interval, an initial nonzero voltage having a first polarity across conductors of the external signaling link, and then conditionally transitions the initial nonzero voltage to a second nonzero voltage according to whether the transmit data bit corresponding to the output-enable interval has a predetermined one of two binary states, the second nonzero voltage having a polarity opposite the first polarity.

    Noise reducing receiver
    6.
    发明授权
    Noise reducing receiver 有权

    公开(公告)号：US11239827B2

    公开(公告)日：2022-02-01

    申请号：US16952553

    申请日：2020-11-19

    Applicant: Rambus Inc.

    Inventor： Masum Hossain ,  Carl W. Werner

    IPC: H03H11/12 ,  H04B1/04 ,  H04B1/58 ,  H04B1/10

    Abstract: Disclosed is receiver for a noise limited system. A front-end circuit amplifies and band-limits an incoming signal. The amplification increases the signal swing but introduces both thermal and flicker noise. A low-pass band limitation reduces the thermal noise component present at frequencies above what is necessary for correctly receiving the transmitted symbols. This band limited signal is provided to the integrator circuit. The output of the integrator is equalized to reduce the effects of inter-symbol interference and then sampled. The samples are used to apply low frequency equalization (i.e., in response to long and/or unbalanced strings of symbols) to mitigate the effects of DC wander caused by mismatches between the number of symbols of each kind being received.

    Low power cryogenic switch
    7.
    发明授权
    Low power cryogenic switch 有权

    公开(公告)号：US11146269B1

    公开(公告)日：2021-10-12

    申请号：US16266244

    申请日：2019-02-04

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Carl W. Werner

    IPC: H03K17/92 ,  H03K19/173 ,  G06F1/26 ,  H03K19/195 ,  F25D29/00

    Abstract: An signal switching integrated-circuit die includes an array of switch cells, control signal contacts, data input contacts and data output contacts. Switch control signals are received from an external control-signal source via respective control signal contacts, inbound data signals are received from one or more external data-signal sources via respective data input contacts and outbound data signals are conveyed to one or more external data-signal destinations via respective data output contacts. The array of switch cells receives the control signals directly from the control signal contacts and response to the control signals by switchably interconnecting the data input contacts with selected ones of the data output contacts.

    DIFFERENTIAL CRYOGENIC TRANSMITTER
    8.
    发明申请
    DIFFERENTIAL CRYOGENIC TRANSMITTER 审中-公开

    公开(公告)号：US20170324019A1

    公开(公告)日：2017-11-09

    申请号：US15478757

    申请日：2017-04-04

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Carl W. Werner

    IPC: H01L39/02

    CPC classification number: H03K3/38 ,  H03K19/017509 ,  H03K19/195

    Abstract: In an integrated-circuit component having a signal transmitter receives a transmitter power supply that cycles periodically between power-off and power-on voltage levels to define a sequence of enable intervals during which the signal transmitter is to output voltage levels corresponding to respective transmit data bits onto an external signaling link. The signal transmitter generates, at the start of each output-enable interval, an initial nonzero voltage having a first polarity across conductors of the external signaling link, and then conditionally transitions the initial nonzero voltage to a second nonzero voltage according to whether the transmit data bit corresponding to the output-enable interval has a predetermined one of two binary states, the second nonzero voltage having a polarity opposite the first polarity.

    LOW POWER SIGNALING INTERFACE
    10.
    发明申请
    LOW POWER SIGNALING INTERFACE 有权

    公开(公告)号：US20230052220A1

    公开(公告)日：2023-02-16

    申请号：US17892291

    申请日：2022-08-22

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Carl W. Werner

    IPC: G11C7/04 ,  G06F1/12 ,  G11C7/22

    Abstract: In a chip-to-chip signaling system includes at least one signaling link coupled between first and second ICs, the first IC has an interface coupled to the signaling link and timed by a first interface timing signal. The second IC has an interface coupled to the signaling link and timed by a second interface timing signal that is mesochronous with respect to the first interface timing signal. The second IC further has phase adjustment circuitry that adjusts a phase of the second interface timing signal using a digital counter implemented with Josephson-junction circuit elements.

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