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    Methods and apparatuses for addressing memory caches
    1.
    发明授权
    Methods and apparatuses for addressing memory caches 有权

    公开(公告)号：US11500781B2

    公开(公告)日：2022-11-15

    申请号：US17107831

    申请日：2020-11-30

    Applicant: Rambus Inc.

    Inventor： Trung Diep ,  Hongzhong Zheng

    IPC: G06F12/00 ,  G06F12/1009 ,  G06F12/0864 ,  G06F12/0811 ,  G11C7/10

    Abstract: A cache memory includes cache lines to store information. The stored information is associated with physical addresses that include first, second, and third distinct portions. The cache lines are indexed by the second portions of respective physical addresses associated with the stored information. The cache memory also includes one or more tables, each of which includes respective table entries that are indexed by the first portions of the respective physical addresses. The respective table entries in each of the one or more tables are to store indications of the second portions of respective physical addresses associated with the stored information.

    Methods and Apparatuses for Addressing Memory Caches
    3.
    发明申请
    Methods and Apparatuses for Addressing Memory Caches 有权

    公开(公告)号：US20210232507A1

    公开(公告)日：2021-07-29

    申请号：US17107831

    申请日：2020-11-30

    Applicant: Rambus Inc.

    Inventor： Trung Diep ,  Hongzhong Zheng

    IPC: G06F12/1009 ,  G06F12/0864 ,  G06F12/0811 ,  G11C7/10

    Abstract: A cache memory includes cache lines to store information. The stored information is associated with physical addresses that include first, second, and third distinct portions. The cache lines are indexed by the second portions of respective physical addresses associated with the stored information. The cache memory also includes one or more tables, each of which includes respective table entries that are indexed by the first portions of the respective physical addresses. The respective table entries in each of the one or more tables are to store indications of the second portions of respective physical addresses associated with the stored information.

    Methods and apparatuses for addressing memory caches
    6.
    发明授权
    Methods and apparatuses for addressing memory caches 有权

    公开(公告)号：US10102140B2

    公开(公告)日：2018-10-16

    申请号：US15393232

    申请日：2016-12-28

    Applicant: RAMBUS INC.

    Inventor： Trung Diep ,  Hongzhong Zheng

    IPC: G06F12/00 ,  G06F12/1009 ,  G06F12/0811

    Abstract: A cache memory includes cache lines to store information. The stored information is associated with physical addresses that include first, second, and third distinct portions. The cache lines are indexed by the second portions of respective physical addresses associated with the stored information. The cache memory also includes one or more tables, each of which includes respective table entries that are indexed by the first portions of the respective physical addresses. The respective table entries in each of the one or more tables are to store indications of the second portions of respective physical addresses associated with the stored information.

    Remapping memory cells based on future endurance measurements
    7.
    发明授权
    Remapping memory cells based on future endurance measurements 有权
    基于未来的耐久性测量重新映射存储单元

    公开(公告)号：US09442838B2

    公开(公告)日：2016-09-13

    申请号：US14058081

    申请日：2013-10-18

    Applicant: Rambus Inc.

    Inventor： Trung Diep ,  John Eric Linstadt ,  J. James Tringali ,  Hongzhong Zheng ,  Brent Steven Haukness

    IPC: G11C13/00 ,  G06F12/02 ,  G11C29/50 ,  G11C29/04

    CPC classification number: G06F12/0238 ,  G06F2212/7204 ,  G06F2212/7211 ,  G11C13/0028 ,  G11C13/0035 ,  G11C13/0069 ,  G11C29/50008 ,  G11C2029/0409 ,  G11C2213/72 ,  G11C2213/79

    Abstract: A method of operating a memory device that includes groups of memory cells is presented. The groups include a first group of memory cells. Each one of the groups has a respective physical address and is initially associated with a respective logical address. The device also includes an additional group of memory cells that has a physical address but is not initially associated with a logical address. In the method, a difference in the future endurance between the first group of memory cells and the additional group of memory cells is identified. When the difference in the future endurance between the first group and the additional group exceeds a predetermined threshold difference, the association between the first group and the logical address initially associated with the first group is ended and the additional group is associated with the logical address that was initially associated with the first group.

    Abstract translation: 提出了一种操作包括存储器单元组的存储器件的方法。 这些组包括第一组记忆单元。 组中的每一个具有相应的物理地址，并且最初与相应的逻辑地址相关联。 该设备还包括具有物理地址但不是最初与逻辑地址相关联的附加组的存储器单元。 在该方法中，识别第一组存储器单元和附加的存储单元组之间的未来耐久性的差异。 当第一组和附加组之间的未来耐久性的差异超过预定阈值差时，第一组和最初与第一组相关联的逻辑地址之间的关联结束，并且附加组与逻辑地址相关联， 最初与第一组有关。

    Wear Leveling in a Memory System
    8.
    发明申请
    Wear Leveling in a Memory System 有权
    在内存系统中磨损调平

    公开(公告)号：US20140372707A1

    公开(公告)日：2014-12-18

    申请号：US14370013

    申请日：2012-12-29

    Applicant: Rambus Inc.

    Inventor： Trung Diep ,  Eric Linstadt

    IPC: G06F12/08 ,  G06F12/10

    CPC classification number: G06F12/0284 ,  G06F3/0616 ,  G06F3/0647 ,  G06F3/0673 ,  G06F12/0246 ,  G06F12/08 ,  G06F12/0891 ,  G06F12/1009 ,  G06F12/126 ,  G06F2212/1036 ,  G06F2212/7211

    Abstract: Embodiments are disclosed for replacing one or more pages of a memory to level wear on the memory. In one embodiment, a system includes a page fault handling function and a memory address mapping function. Upon receipt of a page fault, the page fault handling function maps an evicted virtual memory address to a stressed page and maps a stressed virtual memory address to a free page using the memory address mapping function.

    Abstract translation: 公开了用于替换存储器的一页或多页的级别磨损的实施例。 在一个实施例中，系统包括页面故障处理功能和存储器地址映射功能。 页面错误处理功能在收到页面错误时，将被驱逐的虚拟内存地址映射到应力页面，并使用存储器地址映射功能将压缩的虚拟内存地址映射到空闲页面。

    METHODS AND APPARATUSES FOR ADDRESSING MEMORY CACHES
    9.
    发明申请
    METHODS AND APPARATUSES FOR ADDRESSING MEMORY CACHES 有权
    解决存储器高速缓存的方法和设备

    公开(公告)号：US20130332668A1

    公开(公告)日：2013-12-12

    申请号：US14001464

    申请日：2012-02-22

    Applicant: Rambus Inc.

    Inventor： Trung Diep ,  Hongzhong Zheng

    IPC: G06F12/08 ,  G11C7/10

    CPC classification number: G06F12/1009 ,  G06F12/0811 ,  G06F12/0864 ,  G06F2212/283 ,  G06F2212/656 ,  G11C7/1072

    Abstract: A cache memory includes cache lines to store information. The stored information is associated with physical addresses that include first, second, and third distinct portions. The cache lines are indexed by the second portions of respective physical addresses associated with the stored information. The cache memory also includes one or more tables, each of which includes respective table entries that are indexed by the first portions of the respective physical addresses. The respective table entries in each of the one or more tables are to store indications of the second portions of respective physical addresses associated with the stored information.

    Abstract translation: 缓存存储器包括用于存储信息的高速缓存行。 存储的信息与包括第一，第二和第三不同部分的物理地址相关联。 高速缓存线由与存储的信息相关联的相应物理地址的第二部分索引。 高速缓冲存储器还包括一个或多个表，每个表包括由相应物理地址的第一部分索引的各个表条目。 一个或多个表中的每一个中的相应表条目是存储与存储的信息相关联的相应物理地址的第二部分的指示。

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