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1.发明申请VALIDITY OF ADDRESS RANGES USED IN SEMI-SYNCHRONOUS MEMORY COPY OPERATIONS 有权在同步存储器复制操作中使用的地址范围的有效性公开(公告)号：US20090182968A1
公开(公告)日：2009-07-16
申请号：US12402904
申请日：2009-03-12
申请人： RAVI K. ARIMILLI , Rama K. Govindaraju , Peter H. Hochschild , Bruce G. Mealey , Satya P. Sharma , Balaram Sinharoy
发明人： RAVI K. ARIMILLI , Rama K. Govindaraju , Peter H. Hochschild , Bruce G. Mealey , Satya P. Sharma , Balaram Sinharoy
IPC分类号： G06F12/02
CPC分类号： G06F12/1441 , G06F12/0888 , G06F12/0897
摘要： A system, method, and a computer readable for protecting content of a memory page are disclosed. The method includes determining a start of a semi-synchronous memory copy operation. A range of addresses is determined where the semi-synchronous memory copy operation is being performed. An issued instruction that removes a page table entry is detected. The method further includes determining whether the issued instruction is destined to remove a page table entry associated with at least one address in the range of addresses. In response to the issued instruction being destined to remove the page table entry, the execution of the issued instruction is stalled until the semi-synchronous memory copy operation is completed.
摘要翻译： 公开了一种用于保护存储器页面的内容的系统，方法和可读取的计算机。 该方法包括确定半同步存储器复制操作的开始。 确定正在执行半同步存储器复制操作的地址范围。 检测到发出的删除页表条目的指令。 所述方法还包括确定所发出的指令是否旨在去除与地址范围中的至少一个地址相关联的页表条目。 响应于发出的指令旨在去除页表条目，所发出的指令的执行停止，直到半同步存储器复制操作完成。
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2.发明申请METHOD FOR ENABLING DIRECT PREFETCHING OF DATA DURING ASYCHRONOUS MEMORY MOVE OPERATION 失效用于在异步存储器运行期间实现数据的直接预先提取的方法公开(公告)号：US20090198908A1
公开(公告)日：2009-08-06
申请号：US12024598
申请日：2008-02-01
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F9/30032 , G06F9/3004 , G06F9/30043 , G06F9/30076 , G06F9/30087 , G06F9/3017 , G06F9/30185 , G06F9/3834 , G06F9/3877
摘要： While an AMM operation is ongoing, a prefetch request for data from the source effective address or the destination effective address triggers a cache injection by the AMM mover (or memory controller) of relevant data from the stream of data being moved in the physical memory. The memory controller forwards the first prefetched line to the prefetch engine and L1 cache. The memory controller also forwards the next cache lines in the sequence of data to the L2 cache and a subsequent set of cache lines to the L3 cache. The memory controller then forwards the remaining data to the destination memory location. Quick access to prefetch data is enabled by buffering the stream of data in the upper caches rather than placing all the moved data within the memory. Also, the memory controller does not overrun the upper caches, by placing moved data into only a subset of the available cache lines of the upper level cache.
摘要翻译： 当AMM操作正在进行时，来自源有效地址或目的地有效地址的数据的预取请求触发AMM移动器（或存储器控制器）从在物理存储器中移动的数据流中的相关数据的高速缓存注入。 存储器控制器将第一预取行转发到预取引擎和L1缓存。 存储器控制器还将数据序列中的下一个高速缓存行转发到L2高速缓存以及随后的一组高速缓存行到L3高速缓存。 存储器控制器然后将剩余的数据转发到目的地存储器位置。 通过缓存高速缓存中的数据流，而不是将所有移动的数据放在内存中，可以快速访问预取数据。 此外，通过将移动的数据仅放置在高级缓存的可用高速缓存行的一部分中，存储器控制器不会超过上部高速缓存。
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3.发明申请DATA PROCESSING SYSTEM, PROCESSOR AND METHOD THAT VARY AN AMOUNT OF DATA RETRIEVED FROM MEMORY BASED UPON A HINT 失效数据处理系统，处理器和方法，从基于记忆的记忆中提取的数据量变化不大公开(公告)号：US20090198903A1
公开(公告)日：2009-08-06
申请号：US12024170
申请日：2008-02-01
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F12/0822 , G06F2212/507 , G06F2212/6028
摘要： In at least one embodiment, a processor detects during execution of program code whether a load instruction within the program code is associated with a hint. In response to detecting that the load instruction is not associated with a hint, the processor retrieves a full cache line of data from the memory hierarchy into the processor in response to the load instruction. In response to detecting that the load instruction is associated with a hint, a processor retrieves a partial cache line of data into the processor from the memory hierarchy in response to the load instruction.
摘要翻译： 在至少一个实施例中，处理器在执行程序代码期间检测程序代码内的加载指令是否与提示相关联。 响应于检测到加载指令不与提示相关联，处理器响应于加载指令从存储器层次结构检索完整的高速缓存行数据到处理器。 响应于检测到加载指令与提示相关联，处理器响应于加载指令从存储器层次结构检索数据的部分高速缓存行到处理器中。
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4.发明申请METHOD AND SYSTEM FOR SOURCING DIFFERING AMOUNTS OF PREFETCH DATA IN RESPONSE TO DATA PREFETCH REQUESTS 失效用于根据数据预先要求采集预取数据的不同数据的方法和系统公开(公告)号：US20090198965A1
公开(公告)日：2009-08-06
申请号：US12024165
申请日：2008-02-01
IPC分类号： G06F9/312
CPC分类号： G06F9/383 , G06F9/30043 , G06F9/3455
摘要： According to a method of data processing, a memory controller receives a prefetch load request from a processor core of a data processing system. The prefetch load request specifies a requested line of data. In response to receipt of the prefetch load request, the memory controller determines by reference to a stream of demand requests how much data is to be supplied to the processor core in response to the prefetch load request. In response to the memory controller determining to provide less than all of the requested line of data, the memory controller provides less than all of the requested line of data to the processor core.
摘要翻译： 根据数据处理的方法，存储器控制器从数据处理系统的处理器核心接收预取负载请求。 预取加载请求指定所请求的数据行。 响应于接收到预取加载请求，存储器控制器通过参考需求请求流来确定响应于预取加载请求将多少数据提供给处理器核。 响应于存储器控制器确定提供少于全部所请求的数据行，存储器控制器将少于所有请求的数据行提供给处理器核。
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5.发明申请DATA PROCESSING SYSTEM, PROCESSOR AND METHOD FOR VARYING A DATA PREFETCH SIZE BASED UPON DATA USAGE 有权数据处理系统，用于根据数据使用改变数据预设尺寸的处理器和方法公开(公告)号：US20100293339A1
公开(公告)日：2010-11-18
申请号：US12024163
申请日：2008-02-01
CPC分类号： G06F12/0862 , G06F2212/6024
摘要： A method of data processing in a processor includes maintaining a usage history indicating demand usage of prefetched data retrieved into cache memory. An amount of data to prefetch by a data prefetch request is selected based upon the usage history. The data prefetch request is transmitted to a memory hierarchy to prefetch the selected amount of data into cache memory.
摘要翻译： 一种处理器中的数据处理方法，包括维护指示对高速缓存存储器检索的预取数据的需求使用的使用历史。 基于使用历史来选择由数据预取请求预取的数据量。 将数据预取请求发送到存储器层次结构，以将所选择的数据量预取到高速缓冲存储器中。
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6.发明申请公开(公告)号：US20090198938A1
公开(公告)日：2009-08-06
申请号：US12024575
申请日：2008-02-01
IPC分类号： G06F12/02
CPC分类号： G06F12/10 , G06F9/30032 , G06F9/3834 , G06F9/3861 , G06F12/0815 , G06F12/1027 , G06F13/28
摘要： A method within a data processing system in which a processor handles conflicts, which occur during performance by an asynchronous memory mover of an asynchronous memory move (AMM) operation. The asynchronous memory mover performs an asynchronous memory move (AMM) operation by which the actual data is moved from a source to a destination memory location, independent of the processor. The memory mover sets a flag bit to indicate that the asynchronous memory mover is currently performing an AMM operation at the memory. When the processor receives a memory access operation, the processor checks the value of the flag bit before issuing the new memory access operation, and checks the associated address of the AMM operation to determine possible address conflicts. The processor then evaluates and responds to address conflicts to prevent corruption of data during an AMM operation.
摘要翻译： 数据处理系统中的方法，其中处理器处理由异步存储器移动（AMM）操作的异步存储器移动器执行期间发生的冲突。 异步存储器移动器执行异步存储器移动（AMM）操作，通过该操作将实际数据从源移动到目的地存储器位置，与处理器无关。 存储器移动器设置一个标志位，以指示异步存储器移动器当前在存储器上执行AMM操作。 当处理器接收到存储器访问操作时，处理器在发出新的存储器访问操作之前检查标志位的值，并且检查AMM操作的相关联的地址以确定可能的地址冲突。 然后，处理器评估并响应地址冲突，以防止在AMM操作期间数据损坏。
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7.发明申请DATA PROCESSING SYSTEM, PROCESSOR AND METHOD THAT SUPPORT A TOUCH OF A PARTIAL CACHE LINE OF DATA 审中-公开数据处理系统，处理器和方法，支持部分缓存行数据公开(公告)号：US20090198910A1
公开(公告)日：2009-08-06
申请号：US12024174
申请日：2008-02-01
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F12/0831
摘要： According to method of data processing in a multiprocessor data processing system, in response to a processor touch request targeting a target granule of a cache line of data containing multiple granules, a processing unit originates on an interconnect of the multiprocessor data processing system a partial touch request that requests a copy of only the target granule for subsequent query access. In response to a combined response to the partial touch request indicating success, the combined response representing a system-wide response to the partial touch request, the processing unit receives the target granule of the target cache line and updates a coherency state of the target granule while retaining a coherency state of at least one other granule of the cache line.
摘要翻译： 根据多处理器数据处理系统中的数据处理方法，响应于针对包含多个粒子的数据的高速缓存行的目标颗粒的处理器触摸请求，处理单元起源于多处理器数据处理系统的互连部分触摸 请求仅请求目标颗粒的副本用于后续查询访问。 响应于指示成功的部分触摸请求的组合响应，表示对部分触摸请求的系统范围响应的组合响应，处理单元接收目标高速缓存行的目标颗粒并更新目标颗粒的一致性状态 同时保持高速缓存行的至少另一个颗粒的一致性状态。
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8.发明申请METHOD AND SYSTEM FOR PERFORMING AN ASYNCHRONOUS MEMORY MOVE (AMM) VIA EXECUTION OF AMM STORE INSTRUCTION WITHIN INSTRUCTION SET ARCHITECTURE 有权通过在指令集结构中执行AMM存储指令执行异步存储器移动（AMM）的方法和系统公开(公告)号：US20090198935A1
公开(公告)日：2009-08-06
申请号：US12024494
申请日：2008-02-01
IPC分类号： G06F12/00
CPC分类号： G06F9/30032 , G06F12/0831 , G06F12/0862 , G06F12/10
摘要： A data processing system with a processor and memory includes an instruction set architecture (ISA) that provides an asynchronous memory move (AMM) store (ST) instruction. When the processor executes the AMM ST instruction, the processor performs a series of functions, which initiates an asynchronous memory move (AMM) operation. The AMM ST instruction moves data from a first memory location having a first real address to a second memory location having a second real address by: (a) performing a move of the data in virtual address space utilizing a source effective address that is memory mapped to the first memory location and a destination effective address that is memory mapped to the second memory location. When the move is completed in the virtual address space, the AMM operation performs the physical move of the data to the second memory location outside the processor core, without processor involvement.
摘要翻译： 具有处理器和存储器的数据处理系统包括提供异步存储器移动（AMM）存储（ST）指令的指令集架构（ISA）。 当处理器执行AMM ST指令时，处理器执行一系列功能，其启动异步存储器移动（AMM）操作。 AMM ST指令通过以下方式将数据从具有第一实际地址的第一存储器位置移动到具有第二实际地址的第二存储器位置：（a）使用存储器映射的源有效地址来执行虚拟地址空间中的数据移动 到第一存储器位置和存储器映射到第二存储器位置的目的地有效地址。 当在虚拟地址空间中完成移动时，AMM操作将数据物理移动到处理器核心外部的第二存储器位置，而无需处理器参与。
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公开(公告)号：US20100263855A1
公开(公告)日：2010-10-21
申请号：US12425210
申请日：2009-04-16
IPC分类号： G05D23/00
CPC分类号： G05D23/1931
摘要： A method, system, and computer program product are provided for controlling liquid-cooled electronics, which includes measuring a first set point temperature, Ta, wherein the Ta is based on a dew point temperature, Tdp of a computer room. A second set point temperature, Tb, is measured, wherein the Tb is based on a facility chilled liquid inlet temperature, Tci, and a rack power, Prack, of an electronics rack. A Modular Cooling Unit (MCU) set point temperature, Tsp, is selected. The Tsp is the higher value of said Ta and said Tb. Responsive to the selected Tsp, a control valve is regulated. The control valve controls a flow of liquid that passes through a heat exchanger.
摘要翻译： 提供了一种用于控制液冷电子设备的方法，系统和计算机程序产品，其包括测量第一设定点温度Ta，其中Ta基于计算机室的露点温度Tdp。 测量第二设定点温度Tb，其中Tb基于设备冷冻液体入口温度Tci和电子机架的机架功率Prack。 选择模块化冷却单元（MCU）设定点温度Tsp。 Tsp是较高的Ta值和Tb值。 响应于选定的Tsp，控制阀被调节。 控制阀控制通过热交换器的液体流。
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10.发明申请公开(公告)号：US20100067193A1
公开(公告)日：2010-03-18
申请号：US12425226
申请日：2009-04-16
CPC分类号： H05K7/20809 , H05K7/20745
摘要： Systems and methods are provided for cooling an electronics rack and a computer room from a single unit, which includes a heat-generating electronics subsystem across which air flows from an air inlet to an air outlet side of the rack. First and second modular cooling units (MCUs) are associated with the rack and configured to provide system coolant to the electronics subsystem for cooling thereof. System coolant supply and return manifolds are in fluid communication with the MCUs for facilitating providing of system coolant to the electronics subsystem, and to an air-to-liquid heat exchanger associated with the rack for exclusively cooling air passing through the rack, as well as conditioning the ambient air of the computer room. Such cooling is exclusive of an outside-of-rack conditioned air unit.
摘要翻译： 提供了用于从单个单元冷却电子机架和计算机室的系统和方法，该单元包括发热电子系统，空气从空气入口流到机架的空气出口侧。 第一和第二模块化冷却单元（MCU）与机架相关联并且被配置为向电子子系统提供系统冷却剂用于冷却。 系统冷却剂供应和返回歧管与MCU流体连通，以便于向电子系统提供系统冷却剂，以及与机架相关联的空气 - 液体热交换器，用于专门冷却通过机架的空气，以及 调节计算机房的环境空气。 这种冷却不包括机架外空调单元。
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