公开(公告)号：US20240203812A1

公开(公告)日：2024-06-20

申请号：US18067375

申请日：2022-12-16

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takamichi HOSOKAWA ,  Kazuhiro MITAMURA ,  Fumio MURAKAMI ,  Yuji KAYASHIMA ,  Yoshihiro MASUMURA

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/29 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/315 ,  H01L23/295 ,  H01L23/49838 ,  H01L23/49861 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0655 ,  H01L2224/32245 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48137 ,  H01L2224/48245 ,  H01L2224/73265 ,  H01L2924/1811 ,  H01L2924/1815 ,  H01L2924/182 ,  H01L2924/186 ,  H01L2924/30205 ,  H01L2924/37001

Abstract: A semiconductor device includes a first chip mounting portion, a second chip mounting portion, a first semiconductor chip mounted on the first chip mounting portion, a second semiconductor chip mounted on the second chip mounting portion, a plurality of lead portions, and a sealing portion sealing them. The sealing portion has a first main surface and a second main surface opposite the first main surface. A groove portion is formed in the sealing portion at the first main surface. At the first main surface of the sealing portion, each of the first chip mounting portion and the second chip mounting portion is exposed from the sealing portion. At the first main surface of the sealing portion, the groove portion is formed between an exposed portion of the first chip mounting portion and an exposed portion of the second chip mounting portion.