公开(公告)号：US20170213776A1

公开(公告)日：2017-07-27

申请号：US15515465

申请日：2014-12-24

Applicant: Renesas Electronics Corporation

Inventor： Ryuichi OIKAWA ,  Toshihiko OCHIAI ,  Shuuichi KARIYAZAKI ,  Yuji KAYASHIMA ,  Tsuyoshi KIDA

IPC: H01L23/14 ,  H01L25/065 ,  H01L23/66 ,  H01L23/498

CPC classification number: H01L23/147 ,  H01L23/00 ,  H01L23/32 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49894 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/66 ,  H01L25/065 ,  H01L25/0655 ,  H01L25/07 ,  H01L25/18 ,  H01L2223/6611 ,  H01L2223/6638 ,  H01L2224/16225 ,  H01L2225/06506 ,  H01L2225/06517 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A semiconductor device includes first and second semiconductor components mounted on an interposer mounted on a wiring substrate, and electrically connected to each other via the interposer. Also, a plurality of wiring layers of the interposer include first, second and third wiring layers which are stacked in order from a main surface side to be a reference. In addition, in a first region of the interposer sandwiched between the first semiconductor component and the second semiconductor component, a ratio of a reference potential wiring in the third wiring layer is higher than a ratio of a reference potential wiring in the first wiring layer. Further, in the first region, a ratio of a signal wiring in the first wiring layer is higher than a ratio of a signal wiring in the third wiring layer.

公开(公告)号：US20240203812A1

公开(公告)日：2024-06-20

申请号：US18067375

申请日：2022-12-16

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takamichi HOSOKAWA ,  Kazuhiro MITAMURA ,  Fumio MURAKAMI ,  Yuji KAYASHIMA ,  Yoshihiro MASUMURA

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/29 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/315 ,  H01L23/295 ,  H01L23/49838 ,  H01L23/49861 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0655 ,  H01L2224/32245 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48137 ,  H01L2224/48245 ,  H01L2224/73265 ,  H01L2924/1811 ,  H01L2924/1815 ,  H01L2924/182 ,  H01L2924/186 ,  H01L2924/30205 ,  H01L2924/37001

Abstract: A semiconductor device includes a first chip mounting portion, a second chip mounting portion, a first semiconductor chip mounted on the first chip mounting portion, a second semiconductor chip mounted on the second chip mounting portion, a plurality of lead portions, and a sealing portion sealing them. The sealing portion has a first main surface and a second main surface opposite the first main surface. A groove portion is formed in the sealing portion at the first main surface. At the first main surface of the sealing portion, each of the first chip mounting portion and the second chip mounting portion is exposed from the sealing portion. At the first main surface of the sealing portion, the groove portion is formed between an exposed portion of the first chip mounting portion and an exposed portion of the second chip mounting portion.

公开(公告)号：US20180374788A1

公开(公告)日：2018-12-27

申请号：US16063280

申请日：2016-02-10

Applicant: Renesas Electronics Corporation

Inventor： Kazuyuki NAKAGAWA ,  Katsushi TERAJIMA ,  Keita TSUCHIYA ,  Yoshiaki SATO ,  Hiroyuki UCHIDA ,  Yuji KAYASHIMA ,  Shuuichi KARIYAZAKI ,  Shinji BABA

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065

Abstract: According to an embodiment of the present invention, there is provided a semiconductor device having a first semiconductor component and a second semiconductor component which are mounted on a wiring substrate. The first semiconductor component has a first terminal for transmitting a first signal between the first semiconductor component and the outside and a second terminal for transmitting a second signal between the first semiconductor component and the second semiconductor component. In addition, the second semiconductor component has a third terminal for transmitting the second signal between the second semiconductor component and the first semiconductor component. Further, the first signal is transmitted at a higher frequency than the second signal. Furthermore, the second terminal of the first semiconductor component and the third terminal of the second semiconductor component are electrically connected to each other via the first wiring member. In addition, the first terminal of the first semiconductor component is electrically connected to the wiring substrate via a first bump electrode without the first wiring member interposed therebetween.

公开(公告)号：US20180151460A1

公开(公告)日：2018-05-31

申请号：US15879610

申请日：2018-01-25

Applicant: Renesas Electronics Corporation

Inventor： Ryuichi OIKAWA ,  Toshihiko OCHIAI ,  Shuuichi KARIYAZAKI ,  Yuji KAYASHIMA ,  Tsuyoshi KIDA

IPC: H01L23/14 ,  H01L23/498 ,  H01L25/065 ,  H01L23/66

CPC classification number: H01L23/147 ,  H01L23/00 ,  H01L23/32 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49894 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/66 ,  H01L25/065 ,  H01L25/0655 ,  H01L25/07 ,  H01L25/18 ,  H01L2223/6611 ,  H01L2223/6638 ,  H01L2224/16225 ,  H01L2225/06506 ,  H01L2225/06517 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A semiconductor device includes first and second semiconductor components mounted on an interposer mounted on a wiring substrate, and electrically connected to each other via the interposer. Also, a plurality of wiring layers of the interposer include first, second and third wiring layers which are stacked in order from a main surface side to be a reference. In addition, in a first region of the interposer sandwiched between the first semiconductor component and the second semiconductor component, a ratio of a reference potential wiring in the third wiring layer is higher than a ratio of a reference potential wiring in the first wiring layer. Further, in the first region, a ratio of a signal wiring in the first wiring layer is higher than a ratio of a signal wiring in the third wiring layer.