公开(公告)号：US20240203812A1

公开(公告)日：2024-06-20

申请号：US18067375

申请日：2022-12-16

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takamichi HOSOKAWA ,  Kazuhiro MITAMURA ,  Fumio MURAKAMI ,  Yuji KAYASHIMA ,  Yoshihiro MASUMURA

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/29 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/315 ,  H01L23/295 ,  H01L23/49838 ,  H01L23/49861 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0655 ,  H01L2224/32245 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48137 ,  H01L2224/48245 ,  H01L2224/73265 ,  H01L2924/1811 ,  H01L2924/1815 ,  H01L2924/182 ,  H01L2924/186 ,  H01L2924/30205 ,  H01L2924/37001

Abstract: A semiconductor device includes a first chip mounting portion, a second chip mounting portion, a first semiconductor chip mounted on the first chip mounting portion, a second semiconductor chip mounted on the second chip mounting portion, a plurality of lead portions, and a sealing portion sealing them. The sealing portion has a first main surface and a second main surface opposite the first main surface. A groove portion is formed in the sealing portion at the first main surface. At the first main surface of the sealing portion, each of the first chip mounting portion and the second chip mounting portion is exposed from the sealing portion. At the first main surface of the sealing portion, the groove portion is formed between an exposed portion of the first chip mounting portion and an exposed portion of the second chip mounting portion.

公开(公告)号：US20230402443A1

公开(公告)日：2023-12-14

申请号：US18303902

申请日：2023-04-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshihiro MASUMURA ,  Takamichi HOSOKAWA ,  Keita TAKADA

IPC: H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H01L23/495

CPC classification number: H01L25/18 ,  H01L25/50 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/05 ,  H01L24/06 ,  H01L23/49575 ,  H01L2224/29139 ,  H01L2224/32245 ,  H01L2224/73265 ,  H01L24/92 ,  H01L2224/92247 ,  H01L27/01

Abstract: A semiconductor device includes: a first chip mounting portion; a second chip mounting portion; a first semiconductor chip mounted on the first chip mounting portion; second and third semiconductor chips mounted on the second chip mounting portion; and a sealing body for sealing them. Here, the third semiconductor chip includes a first coil and a second coil that are magnetically coupled to each other. Also, the first coil is electrically connected with a first circuit formed in the first semiconductor chip, and the second coil is electrically connected with a second circuit formed in the second semiconductor chip. Also, in cross-sectional view, the second coil is located closer to the second chip mounting portion than the first coil. Further, a power consumption during an operation of the second semiconductor chip is greater than a power consumption during an operation of the first semiconductor chip.

公开(公告)号：US20240203844A1

公开(公告)日：2024-06-20

申请号：US18482235

申请日：2023-10-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takamichi HOSOKAWA ,  Tatsuaki TSUKUDA ,  Yoshihiro MASUMURA

IPC: H01L23/495 ,  H01F17/00 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49575 ,  H01F17/0006 ,  H01L23/3107 ,  H01L23/49503 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/06177 ,  H01L2224/48245

Abstract: A semiconductor device includes: a first chip mounting portion and a second chip mounting portion adjacent to each other in a first direction; a first semiconductor chip and a third semiconductor chip adjacent to each other in a second direction and mounted on the first chip mounting portion; and a second semiconductor chip mounted on the second chip mounting portion. The third semiconductor has: one or more first transformers used to transmit a signal from the first semiconductor chip to the second semiconductor chip; and one or more second transformers used to transmit a signal from the second semiconductor chip to the first semiconductor chip. In plan view, the first and second transformers are arranged along a side facing the second semiconductor chip, and the one of more first transformers are arranged closer to the first semiconductor chip than the one of more second transformers.