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公开(公告)号：US20200296409A1
公开(公告)日：2020-09-17
申请号：US16811943
申请日：2020-03-06
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Ryoji HASHIMOTO , Seiji MOCHIZUKI
IPC: H04N19/52 , H04N19/176 , H04N19/184 , H04N19/159
Abstract: The decoding method is a decoding method for decoding a bitstream, in which a difference between a reference index and a prediction value of a motion vector is used for each block obtained by dividing each frame of a moving picture in which a plurality of frames are consecutive, in which a plurality of groups having a predetermined number of blocks are defined in each frame and a limitation is applied for each group to a range of reference index and differences of blocks other than the first block in the group, and the decoding method includes a step for determining whether the block to be decoded is the first block of the group, a step for decoding using the reference index and difference if the block is not the first block, and a step for decoding using the limited reference index and differences if the block is not the first block.
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公开(公告)号：US20170094280A1
公开(公告)日：2017-03-30
申请号：US15266528
申请日：2016-09-15
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Ren IMAOKA , Seiji MOCHIZUKI , Toshiyuki KAYA , Kazushi AKIE , Ryoji HASHIMOTO
IPC: H04N19/139 , H04N19/61 , H04N19/124 , H04N19/42 , H04N19/105 , H04N19/159
CPC classification number: H04N19/139 , H04N19/105 , H04N19/124 , H04N19/132 , H04N19/137 , H04N19/159 , H04N19/172 , H04N19/174 , H04N19/186 , H04N19/439 , H04N19/61
Abstract: A semiconductor device includes a hash generator, a reference hash list, a frame mode determination unit, and an intra prediction unit. The hash generator generates a hash value of a target frame to be encoded. The reference hash list is to record the hash value generated by the hash generator. The frame mode determination unit compares the hash value generated by the hash generator and the hash value in the reference hash list. The intra prediction unit performs intra prediction for the target frame to be encoded. When the hash value of the target frame to be encoded coincides with any of the hash values in the reference hash list, the intra prediction unit skips an encoding process, and outputs encoded information corresponding to any of the hash values in the reference hash list.
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公开(公告)号：US20180253127A1
公开(公告)日：2018-09-06
申请号：US15858361
申请日：2017-12-29
Applicant: Renesas Electronics Corporation
Inventor： Hiroshi UEDA , Ryoji HASHIMOTO , Taku MAEKAWA , Katsushige MATSUBARA , Keisuke MATSUMOTO
Abstract: A CPU needs to perform reset operation when a secondary arithmetic processing unit controlled by the CPU controls a signal processing circuit. CPU A controls module A. CPU B controls module B. Module A and module B control a signal processing circuit. CPU A and CPU B issue a reset request to the signal processing circuit. The signal processing circuit performs a reset process based on the reset request accepted from the CPU and a control origin identification signal that identifies a CPU as an origin of controlling the module having started a signal processing section.
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公开(公告)号：US20170039160A1
公开(公告)日：2017-02-09
申请号：US14915621
申请日：2015-03-12
Applicant: Renesas Electronics Corporation
Inventor： Takahiko SUGIMOTO , Tomohiro UNE , Hiroshi UEDA , Ryoji HASHIMOTO , Toshiyuki KAYA
CPC classification number: G06F13/4221 , G06F13/00 , G06F13/4009 , G06F13/4027
Abstract: A data selector circuit divides a group of data including a plurality of types of data into the plurality of types of data. A first compression circuit and a second compression circuit respectively compress the plurality of types of data in parallel with each other in accordance with each of the plurality of types of data. The first compression circuit compresses data and obtains compressed data. The second compression circuit compresses data and obtains compressed data. The data transmission circuit-transmits the compressed data and the compressed data to a terminal.
Abstract translation: 数据选择器电路将包括多种类型的数据的数据组划分成多种类型的数据。 第一压缩电路和第二压缩电路根据多种类型的数据分别彼此并行地压缩多种类型的数据。 第一压缩电路压缩数据并获得压缩数据。 第二压缩电路压缩数据并获得压缩数据。 数据传输电路将压缩数据和压缩数据发送到终端。
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公开(公告)号：US20210294691A1
公开(公告)日：2021-09-23
申请号：US16821915
申请日：2020-03-17
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Katsushige MATSUBARA , Ryoji HASHIMOTO , Takahiro IRITA , Kenichi SHIMADA , Tetsuya SHIBAYAMA
Abstract: In a data processing device comprising a memory controller controlling writing/reading of data to/from the memory, a processor requesting writing/reading of data, and an error detection module requesting writing/reading of data to/from the memory controller in accordance with a request from the processor, an error detection module calculates a first error detection code of the first data having a write request from the processor, reads the second data having a read request from the processor from the memory, calculates a second error detection code from the read data, compares the first error detection code and the second error detection code, and transmits the result of the comparison to the external module.
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Patent Agency Ranking
公开(公告)号：US20180288418A1
公开(公告)日：2018-10-04
申请号：US16001559
申请日：2018-06-06
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Ren IMAOKA , Seiji MOCHIZUKI , Toshiyuki KAYA , Kazushi AKIE , Ryoji HASHIMOTO
IPC: H04N19/139 , H04N19/137 , H04N19/132 , H04N19/172 , H04N19/124 , H04N19/105 , H04N19/61
Abstract: A semiconductor device includes a hash generator, a reference hash list, a frame mode determination unit, and an intra prediction unit. The hash generator generates a hash value of a target frame to be encoded. The reference hash list is to record the hash value generated by the hash generator. The frame mode determination unit compares the hash value generated by the hash generator and the hash value in the reference hash list. The intra prediction unit performs intra prediction for the target frame to be encoded. When the hash value of the target frame to be encoded coincides with any of the hash values in the reference hash list, the intra prediction unit skips an encoding process, and outputs encoded information corresponding to any of the hash values in the reference hash list.
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7.发明申请公开(公告)号：US20180077413A1
公开(公告)日：2018-03-15
申请号：US15699801
申请日：2017-09-08
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Kazushi AKIE , Seiji MOCHIZUKI , Toshiyuki KAYA , Katsushige MATSUBARA , Hiroshi UEDA , Ren IMAOKA , Ryoji HASHIMOTO
IPC: H04N19/107 , H04N19/105 , H04N19/44 , H04N19/122 , H04N19/436 , H04N19/573 , H04N19/17 , G06T9/00
CPC classification number: H04N19/107 , G06T9/007 , H04N19/105 , H04N19/122 , H04N19/17 , H04N19/436 , H04N19/44 , H04N19/573 , H04N21/4728 , H04N21/816
Abstract: A display area can be smoothly moved.A semiconductor device sequentially receives a plurality of whole images, each of which includes a plurality of small screen images and which are temporally continuous and form a moving image, and decodes a received whole image. Here, the semiconductor device includes a reception unit that receives the whole image including the small screen images, a determination unit that determines a decoding area which includes a small screen image to be decoded and which is included in the whole image, and a decoding unit that decodes the small screen image in the decoding area which is determined by the determination unit and which is included in the whole image. The determination unit determines a new decoding area when a small screen image of intra frame appears in the decoding area.
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公开(公告)号：US20170280155A1
公开(公告)日：2017-09-28
申请号：US15618316
申请日：2017-06-09
Applicant: Renesas Electronics Corporation
Inventor： Kenichi IWATA , Seiji MOCHIZUKI , Toshiyuki KAYA , Ryoji HASHIMOTO
IPC: H04N19/513 , H04N19/174 , H04N19/55 , H04N19/105 , H04N19/167
CPC classification number: H04N19/521 , H04N19/105 , H04N19/167 , H04N19/174 , H04N19/436 , H04N19/51 , H04N19/55 , H04N19/86
Abstract: To reduce noise or the like generated at a boundary of tiles introduced in a video coding method. In a motion vector detection unit, a first tile video signal and a second tile video signal included in one picture are supplied to a first detection unit and a second detection unit, and a reference image is supplied from a frame memory to the first detection unit and the second detection unit. The first detection unit performs processing, by inter prediction, on the video signal positioned on or in the vicinity of a tile boundary between a first tile and another tile among many video signals included in the first tile. In this processing, the first detection unit generates a motion vector so as to preferentially refer to the reference image included in another tile different from the first tile among the reference images read out from the frame memory.
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公开(公告)号：US20170366817A1
公开(公告)日：2017-12-21
申请号：US15697143
申请日：2017-09-06
Applicant: Renesas Electronics Corporation
Inventor： Ryoji HASHIMOTO , Seiji MOCHIZUKI , Kenichi IWATA
IPC: H04N19/159 , H04N19/593 , H04N19/176 , H04N19/105 , H04N19/119 , H04N19/11 , H04N19/70 , H04N19/50
CPC classification number: H04N19/159 , H04N19/105 , H04N19/11 , H04N19/119 , H04N19/176 , H04N19/50 , H04N19/593 , H04N19/70
Abstract: In terms of the transmission of the coding method, it is ensured to decode information coded according to the intra-frame prediction coding with vector information. An error of a piece of divisional image information targeted for image prediction coding and a piece of predicted information is determined to perform prediction coding. A data stream in which a piece of information for identifying a prediction method and a piece of information subjected to prediction coding according to the method are arranged is produced according to the process sequence of the prediction coding for each process on the divisional image information. At this time, the data stream has a pair of vector information and the error information as information subjected to prediction coding for each process on the divisional image information on condition that the prediction method is intra-frame prediction coding with vectors.
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公开(公告)号：US20170264820A1
公开(公告)日：2017-09-14
申请号：US15421503
申请日：2017-02-01
Applicant: Renesas Electronics Corporation
Inventor： Tetsuya SHIBAYAMA , Toshiyuki KAYA , Seiji MOCHIZUKI , Ryoji HASHIMOTO
IPC: H04N5/232 , H04N19/124 , H04N19/20
Abstract: A semiconductor device includes: an encoding processing unit that stores an encoded stream of an input data that is encoded based on the specified encoding control information; a buffer management unit that calculates the transmission buffer occupancy indicating the amount of data stored in a transmission buffer according to the generated data amount, and the reception buffer occupancy indicating the amount of data stored in a reception buffer, which is the destination of the encoded stream; and a control information specifying unit that, when the transmission buffer occupancy is equal to or less than a first threshold, specifies the encoding control information based on the reception buffer occupancy, and when the transmission buffer occupancy is greater than the first threshold, specifies the encoding control information to further reduce the generated data amount than in the case of equal to or less than the first threshold, to the encoding processing unit.
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