公开(公告)号：US20240063059A1

公开(公告)日：2024-02-22

申请号：US18142825

申请日：2023-05-03

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koichi ANDO ,  Toshiyuki HATA ,  Kosuke KITAICHI ,  Hiroi OKA

IPC: H01L21/784 ,  H01L29/06 ,  H01L29/66 ,  H01L21/66

CPC classification number: H01L21/784 ,  H01L29/0649 ,  H01L29/66712 ,  H01L22/30 ,  H01L22/12

Abstract: In a case where a crack occurs in a dicing step, the crack can be suppressed from proceeding toward an element region. A first scribe region and a second scribe region that both define an element region are formed in a main surface of a semiconductor wafer. In the first scribe region, an evaluation-deep-trench group including an evaluation-deep-trench-first portion and an evaluation-deep-trench-second portion is formed. The evaluation-deep-trench-first portion is formed in a first region. The evaluation-deep-trench-second portion has a width in an X-axis direction, and is formed in a bar shape extending in a Y-axis direction, in a second region located between the first region and the element region.

公开(公告)号：US20210167012A1

公开(公告)日：2021-06-03

申请号：US16700485

申请日：2019-12-02

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shunji KUBO ,  Koichi ANDO ,  Eiji IO ,  Hideyuki TAJIMA ,  Tetsuya IIDA

IPC: H01L23/522 ,  H01L23/373

Abstract: A semiconductor device includes a base member, a multilayer wiring layer, and a first resistive element. The multilayer wiring layer is formed on the base member. The first resistive element is formed in the multilayer wiring layer. The first resistive element includes a first conductive part, a second conductive part and a third conductive part. The second conductive part is formed over the first conductive part. The third conductive part electrically connects the first conductive part and the second conductive part with each other. A length of the third conductive part in a first direction along a surface of the base member is greater than a length of the third conductive part in a second direction along the surface of the base member and perpendicular to the first direction.

公开(公告)号：US20180067793A1

公开(公告)日：2018-03-08

申请号：US15650282

申请日：2017-07-14

Applicant: Renesas Electronics Corporation

Inventor： Tomoya SAITO ,  Masamichi FUJITO ,  Koichi ANDO ,  Takashi HASHIMOTO

IPC: G06F11/07

CPC classification number: G06F11/0727 ,  G06F11/073 ,  G06F11/0793 ,  G06F2212/72 ,  G11C16/28 ,  G11C16/3431 ,  G11C29/50004

Abstract: The present invention aims at providing a flash memory that can perform a refresh operation at an appropriate time before a read error occurs. The controller performs the first read operation in which the memory cell as the read target is made to draw out the potential of one of the bit lines, the bit line potential controller is made to draw out the potential of the other of the bit lines at the first speed, and concurrently, the sense amplifier is made to read data; the second read operation in which the memory cell as the read target is made to draw out the potential of one of the bit lines, the bit line potential controller is made to draw out the potential of the other of the bit lines at the second speed faster than the first speed, and concurrently, the sense amplifier is made to read data; and the refresh operation in which, when the data read by the first read operation and the data read by the second read operation are determined to be different, the data stored in the memory cell as the read target is rewritten.