Patent search ap:("RENESAS ELECTRONICS CORPORATION") AND inv:"Hiroi OKA" Page 1

1.

发明申请
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开

公开(公告)号：US20170287765A1

公开(公告)日：2017-10-05

申请号：US15628537

申请日：2017-06-20

Applicant: Renesas Electronics Corporation

Inventor： Takamitsu YOSHIHARA , Takahiro KAINUMA , Hiroi OKA

IPC: H01L21/683 , H01L23/00 , H01L23/495 , H01L21/304 , H01L21/78

CPC classification number: H01L21/6836 , H01L21/304 , H01L21/3043 , H01L21/78 , H01L23/49524 , H01L23/49562 , H01L23/49582 , H01L24/34 , H01L24/37 , H01L2221/68327 , H01L2221/6834 , H01L2221/68386 , H01L2224/37147 , H01L2224/37599 , H01L2224/83801 , H01L2224/8385 , H01L2224/84801 , H01L2224/8485 , H01L2924/00014

Abstract: Provided is a method of manufacturing a semiconductor device with improved manufacturing efficiency for the semiconductor device. The method of manufacturing a semiconductor device includes the steps of: (a) forming a circuit at a front surface side of a wafer (semiconductor wafer) having the front surface and a back surface opposite to the front surface; (b) grinding the back surface of the wafer that has a center part (first part) and a peripheral edge part (second part) surrounding a periphery of the center part in such a manner that the center part is thinner than the peripheral edge part; (c) attaching an upper surface (bonding surface) of a holding tape to the front surface of the wafer; and (d) separating the center part from the peripheral edge part by cutting a part of the center part with a blade (rotary blade) while the wafer is held by the first tape.

2.

发明公开
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开

公开(公告)号：US20240063059A1

公开(公告)日：2024-02-22

申请号：US18142825

申请日：2023-05-03

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koichi ANDO , Toshiyuki HATA , Kosuke KITAICHI , Hiroi OKA

IPC: H01L21/784 , H01L29/06 , H01L29/66 , H01L21/66

CPC classification number: H01L21/784 , H01L29/0649 , H01L29/66712 , H01L22/30 , H01L22/12

Abstract: In a case where a crack occurs in a dicing step, the crack can be suppressed from proceeding toward an element region. A first scribe region and a second scribe region that both define an element region are formed in a main surface of a semiconductor wafer. In the first scribe region, an evaluation-deep-trench group including an evaluation-deep-trench-first portion and an evaluation-deep-trench-second portion is formed. The evaluation-deep-trench-first portion is formed in a first region. The evaluation-deep-trench-second portion has a width in an X-axis direction, and is formed in a bar shape extending in a Y-axis direction, in a second region located between the first region and the element region.

3.

发明申请
Semiconductor Device 审中-公开
Title translation: 半导体器件

公开(公告)号：US20130207252A1

公开(公告)日：2013-08-15

申请号：US13846730

申请日：2013-03-18

Applicant: Renesas Electronics Corporation

Inventor： Kuniharu MUTO , Toshiyuki HATA , Hiroshi SATO , Hiroi OKA , Osamu IKEDA

IPC: H01L23/495

CPC classification number: H01L23/49582 , H01L23/49503 , H01L23/49524 , H01L23/49548 , H01L23/49562 , H01L23/544 , H01L24/05 , H01L24/29 , H01L24/35 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/77 , H01L24/78 , H01L24/83 , H01L24/84 , H01L24/85 , H01L29/0615 , H01L29/41766 , H01L29/456 , H01L29/7397 , H01L29/7811 , H01L29/7813 , H01L2223/54406 , H01L2223/54433 , H01L2223/54486 , H01L2224/04042 , H01L2224/05073 , H01L2224/05166 , H01L2224/05624 , H01L2224/0603 , H01L2224/29294 , H01L2224/29339 , H01L2224/32245 , H01L2224/37124 , H01L2224/40091 , H01L2224/40245 , H01L2224/40247 , H01L2224/4103 , H01L2224/45014 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/4846 , H01L2224/48465 , H01L2224/48624 , H01L2224/48724 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/4912 , H01L2224/73219 , H01L2224/73221 , H01L2224/73265 , H01L2224/78 , H01L2224/83801 , H01L2224/8385 , H01L2224/84205 , H01L2224/85205 , H01L2224/85207 , H01L2224/85214 , H01L2924/00011 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01054 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/10253 , H01L2924/12042 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19043 , H01L2924/00014 , H01L2924/00012 , H01L2924/00 , H01L2924/3512 , H01L2224/83205 , H01L2924/206

Abstract: To actualize a reduction in the on-resistance of a small surface mounted package having a power MOSFET sealed therein. A silicon chip is mounted on a die pad portion integrated with leads configuring a drain lead. The silicon chip has, on the main surface thereof, a source pad and a gate pad. The backside of the silicon chip configures a drain of a power MOSFET and bonded to the upper surface of a die pad portion via an Ag paste. A lead configuring a source lead is electrically coupled to the source pad via an Al ribbon, while a lead configuring a gate lead is electrically coupled to the gate pad via an Au wire.

Abstract translation: 实现密封在其中的功率MOSFET的小型表面安装封装的导通电阻的降低。硅芯片安装在与构成漏极引线的引线集成的管芯焊盘部分上。硅芯片在其主表面上具有源极焊盘和栅极焊盘。硅芯片的背面配置功率MOSFET的漏极，并通过Ag浆料粘合到芯片焊盘部分的上表面。构成源极引线的引线通过Al带电耦合到源极焊盘，而构成栅极引线的引线通过Au线电耦合到栅极焊盘。

4.

发明申请
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开

公开(公告)号：US20170221800A1

公开(公告)日：2017-08-03

申请号：US15515297

申请日：2015-03-30

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi NISHIKIZAWA , Yuichi YATO , Hiroi OKA , Tadatoshi DANNO , Hiroyuki NAKAMURA

IPC: H01L23/495 , H01L21/48 , H01L21/56 , H01L23/31

CPC classification number: H01L23/49513 , H01L21/4825 , H01L21/565 , H01L23/3107 , H01L23/3114 , H01L23/4952 , H01L23/49562 , H01L23/49568 , H01L23/49575 , H01L24/06 , H01L2224/05554 , H01L2224/32245 , H01L2224/45144 , H01L2224/48137 , H01L2224/48247 , H01L2224/73265 , H01L2224/83192 , H01L2224/92247 , H01L2924/181 , H01L2924/00012 , H01L2924/00

Abstract: In a resin sealing type semiconductor device, a semiconductor chip CP2 is mounted over a die pad DP having conductivity via a bonding member BD2 having insulation property, and a semiconductor chip CP1 is mounted over the die pad DP via a bonding member BD1 having conductivity. A first length of a portion, in a first side formed by an intersection of a first side surface and a second side surface of the semiconductor chip CP2, covered with the bonding member BD2 is larger than a second length of a portion, in a second side formed by an intersection of a third side surface and a fourth side surface of the semiconductor chip CP1, covered with the bonding member BD1.

5.

发明申请
Method For Manufacturing Semiconductor Device 有权
Title translation: 制造半导体器件的方法

公开(公告)号：US20160293473A1

公开(公告)日：2016-10-06

申请号：US15007275

申请日：2016-01-27

Applicant: Renesas Electronics Corporation

Inventor： Takamitsu YOSHIHARA , Takahiro KAINUMA , Hiroi OKA

IPC: H01L21/683 , H01L21/78 , H01L23/544 , H01L21/304

CPC classification number: H01L21/6836 , H01L21/304 , H01L21/3043 , H01L21/78 , H01L23/49524 , H01L23/49562 , H01L23/49582 , H01L24/34 , H01L24/37 , H01L2221/68327 , H01L2221/6834 , H01L2221/68386 , H01L2224/37147 , H01L2224/37599 , H01L2224/83801 , H01L2224/8385 , H01L2224/84801 , H01L2224/8485 , H01L2924/00014

Abstract: Provided is a method of manufacturing a semiconductor device with improved manufacturing efficiency for the semiconductor device. The method of manufacturing a semiconductor device includes the steps of: (a) forming a circuit at a front surface side of a wafer (semiconductor wafer) having the front surface and a back surface opposite to the front surface; (b) grinding the back surface of the wafer that has a center part (first part) and a peripheral edge part (second part) surrounding a periphery of the center part in such a manner that the center part is thinner than the peripheral edge part; (c) attaching an upper surface (bonding surface) of a holding tape to the front surface of the wafer; and (d) separating the center part from the peripheral edge part by cutting a part of the center part with a blade (rotary blade) while the wafer is held by the first tape.

Abstract translation: 提供一种制造半导体器件的制造效率提高的半导体器件的方法。制造半导体器件的方法包括以下步骤：（a）在具有与前表面相对的前表面和后表面的晶片（半导体晶片）的正面侧形成电路; （b）研磨具有中心部分（第一部分）的晶片的背面和围绕中心部分周围的周缘部分（第二部分），使得中心部分比周缘部分薄 ; （c）将保持带的上表面（接合面）附接到晶片的前表面; 以及（d）通过在由第一带保持晶片的同时用刀片（旋转刀片）切割中心部分的一部分来将中心部分与周边部分分离。

6.

发明申请
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开

公开(公告)号：US20180315685A1

公开(公告)日：2018-11-01

申请号：US16020353

申请日：2018-06-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi NISHIKIZAWA , Yuichi YATO , Hiroi OKA , Tadatoshi DANNO , Hiroyuki NAKAMURA

IPC: H01L23/495 , H01L21/56 , H01L21/48 , H01L23/31 , H01L23/00

CPC classification number: H01L23/49513 , H01L21/4825 , H01L21/565 , H01L23/3107 , H01L23/3114 , H01L23/4952 , H01L23/49562 , H01L23/49568 , H01L23/49575 , H01L24/06 , H01L2224/05554 , H01L2224/32245 , H01L2224/45144 , H01L2224/48137 , H01L2224/48247 , H01L2224/73265 , H01L2224/83192 , H01L2224/92247 , H01L2924/181 , H01L2924/00012 , H01L2924/00

Abstract: In a resin sealing type semiconductor device, a semiconductor chip CP2 is mounted over a die pad DP having conductivity via a bonding member BD2 having insulation property, and a semiconductor chip CP1 is mounted over the die pad DP via a bonding member BD1 having conductivity. A first length of a portion, in a first side formed by an intersection of a first side surface and a second side surface of the semiconductor chip CP2, covered with the bonding member BD2 is larger than a second length of a portion, in a second side formed by an intersection of a third side surface and a fourth side surface of the semiconductor chip CP1, covered with the bonding member BD1.

7.

发明申请
SEMICONDUCTOR DEVICE 有权
Title translation: 半导体器件

公开(公告)号：US20160204057A1

公开(公告)日：2016-07-14

申请号：US14901424

申请日：2013-07-05

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuichi YATO , Hiroi OKA , Noriko OKUNISHI , Keita TAKADA

IPC: H01L23/498 , H01L23/31 , H01L23/13

CPC classification number: H01L23/49513 , H01L21/565 , H01L23/13 , H01L23/16 , H01L23/24 , H01L23/3121 , H01L23/3142 , H01L23/4952 , H01L23/49524 , H01L23/49541 , H01L23/49548 , H01L23/49562 , H01L23/49582 , H01L23/49805 , H01L23/49844 , H01L23/562 , H01L24/05 , H01L24/06 , H01L24/29 , H01L24/32 , H01L24/37 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/743 , H01L24/77 , H01L2224/05624 , H01L2224/05644 , H01L2224/0603 , H01L2224/2929 , H01L2224/29339 , H01L2224/32245 , H01L2224/37147 , H01L2224/40091 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/45014 , H01L2224/45124 , H01L2224/45144 , H01L2224/48247 , H01L2224/48624 , H01L2224/48644 , H01L2224/73221 , H01L2224/73263 , H01L2224/73265 , H01L2224/743 , H01L2224/83192 , H01L2224/83439 , H01L2224/8385 , H01L2224/83862 , H01L2224/84205 , H01L2224/84439 , H01L2224/8501 , H01L2224/85181 , H01L2224/85205 , H01L2224/85439 , H01L2224/92157 , H01L2224/92247 , H01L2924/00014 , H01L2924/1301 , H01L2924/13091 , H01L2924/15747 , H01L2924/181 , H01L2924/18301 , H01L2924/351 , H01L2924/00 , H01L2924/0665 , H01L2924/00012 , H01L2224/45015 , H01L2924/207

Abstract: A semiconductor device according to an embodiment is a semiconductor device in which a semiconductor chip mounted on a chip mounting part is sealed by resin and a first member is fixed to a chip mounting surface side between a peripheral portion of the semiconductor chip and a peripheral portion of the chip mounting part. Also, the first member is sealed by the resin. Also, a length of the first part of the chip mounting part in the first direction is larger than a length of the semiconductor chip in the first direction, in a plan view.

Abstract translation: 根据实施例的半导体器件是半导体器件，其中安装在芯片安装部分上的半导体芯片被树脂密封，并且第一构件固定到半导体芯片的周边部分与周边部分之间的芯片安装表面侧的芯片安装部分。此外，第一构件被树脂密封。此外，芯片安装部分的第一方向的第一部分的长度在平面图中大于半导体芯片沿第一方向的长度。

8.

发明申请
MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE 审中-公开

公开(公告)号：US20190006268A1

公开(公告)日：2019-01-03

申请号：US15985957

申请日：2018-05-22

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Masatoshi SUGIURA , Hiroi OKA

IPC: H01L23/495 , H01L23/00 , H01L21/48

CPC classification number: H01L23/49568 , H01L21/4825 , H01L23/49513 , H01L23/49524 , H01L23/49562 , H01L23/562 , H01L24/08 , H01L24/45 , H01L24/48 , H01L2224/0603 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48247 , H01L2224/48472 , H01L2224/4903 , H01L2224/73265 , H01L2224/83192 , H01L2224/92247 , H01L2924/13055 , H01L2924/181 , H01L2924/3511 , H01L2924/00012 , H01L2924/00 , H01L2924/00014

Abstract: A die bonding process for assembling a semiconductor device includes the steps of applying a sintered-silver-use paste to each of a plurality of first regions on an upper surface of a chip mounting part, drying the sintered-silver-use paste and applying a silver paste to a second region located between/among the respective first regions. Further, the process includes the step of mounting a semiconductor chip onto the chip mounting part in such a manner that a rear surface of the semiconductor chip faces an upper surface of the chip mounting part with the sintered-silver-use paste and the silver paste being interposed. After mounting the chip, part of each of first, second, third and fourth corners of a principal surface of the semiconductor chip is located in each of the first regions.

9.

发明申请
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开

公开(公告)号：US20180247884A1

公开(公告)日：2018-08-30

申请号：US15558977

申请日：2015-07-23

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazunori HASEGAWA , Hiroi OKA

IPC: H01L23/495 , H01L23/31 , H01L23/00 , H01L21/48

CPC classification number: H01L23/49513 , H01L21/4825 , H01L21/52 , H01L23/3114 , H01L23/49524 , H01L23/49562 , H01L23/49575 , H01L24/29 , H01L24/32 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/83 , H01L2224/0603 , H01L2224/29139 , H01L2224/32245 , H01L2224/371 , H01L2224/37147 , H01L2224/37599 , H01L2224/40137 , H01L2224/40139 , H01L2224/40245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48245 , H01L2224/48247 , H01L2224/49171 , H01L2224/73221 , H01L2224/73263 , H01L2224/73265 , H01L2224/83002 , H01L2224/83192 , H01L2224/8384 , H01L2924/1203 , H01L2924/13055 , H01L2924/14252 , H01L2924/181 , H01L2924/00012 , H01L2924/00014 , H01L2924/00

Abstract: Reliability of a semiconductor device is improved. For this, embodied is a basic idea that a semiconductor chip (CHP1) mounted on an Ag layer (AGL) is fixed by using a temporarily fixing material (TA) having tackiness without forming the temporarily fixing material (TA) on a surface of the Ag layer (AGL) having a porous structure as much as possible, is realized. More specifically, the temporarily fixing material (TA) is supplied so as to have a portion made in contact with a chip mounting part (TAB), and the semiconductor chip (CHP1) is also mounted on the Ag layer (AGL) so that one portion of a rear surface of the semiconductor chip (CHP1) is made in contact with the temporarily fixing material (TA).