公开(公告)号：US20240170346A1

公开(公告)日：2024-05-23

申请号：US18452822

申请日：2023-08-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kosuke KITAICHI

IPC: H01L21/66 ,  H01L21/78 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L22/14 ,  H01L21/78 ,  H01L29/402 ,  H01L29/66348

Abstract: In a wafer test step, a dummy semiconductor element formed in a scribe region of a semiconductor substrate is inspected by using a testing electrode provided in the scribe region and electrically connected to the dummy semiconductor element. In a dicing step, the scribe region of the semiconductor substrate is cut by using a dicing blade. The testing electrode includes a plurality of pad portions and a plurality of connection portions connecting the plurality of pad portions to each other. A width of each of the plurality of connection portions is larger than a width of the dicing blade, and smaller than a width of each of the plurality of pad portions. In plan view, the plurality of pad portions is arranged in a linear manner in a moving direction of the dicing blade, and the plurality of connection portions is arranged in a staggered manner in the moving direction.

公开(公告)号：US20240063059A1

公开(公告)日：2024-02-22

申请号：US18142825

申请日：2023-05-03

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koichi ANDO ,  Toshiyuki HATA ,  Kosuke KITAICHI ,  Hiroi OKA

IPC: H01L21/784 ,  H01L29/06 ,  H01L29/66 ,  H01L21/66

CPC classification number: H01L21/784 ,  H01L29/0649 ,  H01L29/66712 ,  H01L22/30 ,  H01L22/12

Abstract: In a case where a crack occurs in a dicing step, the crack can be suppressed from proceeding toward an element region. A first scribe region and a second scribe region that both define an element region are formed in a main surface of a semiconductor wafer. In the first scribe region, an evaluation-deep-trench group including an evaluation-deep-trench-first portion and an evaluation-deep-trench-second portion is formed. The evaluation-deep-trench-first portion is formed in a first region. The evaluation-deep-trench-second portion has a width in an X-axis direction, and is formed in a bar shape extending in a Y-axis direction, in a second region located between the first region and the element region.

公开(公告)号：US20230378032A1

公开(公告)日：2023-11-23

申请号：US18175805

申请日：2023-02-28

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kosuke KITAICHI ,  Masatoshi SUGIURA ,  Hideaki TAMIMOTO ,  Takehiko MAEDA ,  Keita TAKADA ,  Yoshitaka KYOUGOKU

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H02M7/00

CPC classification number: H01L23/49562 ,  H01L24/32 ,  H01L24/73 ,  H01L23/49513 ,  H01L24/48 ,  H01L23/3142 ,  H01L21/565 ,  H01L23/4952 ,  H01L23/49582 ,  H02M7/003 ,  H01L24/83 ,  H01L2224/48247 ,  H01L2224/32245 ,  H01L2224/73265 ,  H01L2924/30101 ,  H01L2924/13091 ,  H01L2224/83862

Abstract: To manufacture a semiconductor device, a first heat treatment for curing a first adhesive material of a conductive paste type is performed, after a semiconductor chip is mounted on a die pad of a lead frame via the first adhesive material. After that, a metal plate is disposed on a pad of the semiconductor chip such that the metal plate faces the pad of the semiconductor chip via a second adhesive material of a conductive paste type, and a second heat treatment is performed for curing each of the first adhesive material and the second adhesive material. A time of the first heat treatment is less than a time of the second heat treatment. After the first adhesive material is cured by the first heat treatment, the first adhesive material is further cured by the second heat treatment.