公开(公告)号：US20190304544A1

公开(公告)日：2019-10-03

申请号：US16352273

申请日：2019-03-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tomoya SAITO ,  Naoki TAKIZAWA

IPC: G11C16/14 ,  G11C16/26 ,  G11C16/04

Abstract: It is to optimize the initial threshold voltages of each memory area in a semiconductor memory device including a plurality of memory areas. A semiconductor memory device according to the embodiment includes a first memory area for storing data and a second memory area for storing the information related to the first memory area. In the respective memory cells arranged in the first and the second memory areas, the initial threshold voltages of the memory cells arranged in the second memory area are designed to be higher than those of the memory cells arranged in the first memory area.

公开(公告)号：US20180329770A1

公开(公告)日：2018-11-15

申请号：US16032306

申请日：2018-07-11

Applicant: Renesas Electronics Corporation

Inventor： Tomoya SAITO ,  Masamichi FUJITO ,  KOICHI ANDO ,  Takashi HASHIMOTO

IPC: G06F11/07 ,  G11C16/34 ,  G11C29/50 ,  G11C16/28

CPC classification number: G06F11/0727 ,  G06F11/073 ,  G06F11/0793 ,  G06F2212/72 ,  G11C16/28 ,  G11C16/3431 ,  G11C29/50004

Abstract: A flash memory refreshes at a time before a read error might occur. A controller performs a first read operation and a second read operation using a sense amplifier. In the second read operation, a bit line potential controller draws out a potential of a bit line feeding the sense amplifier so that, if memory cell degradation has occurred, the degradation can be detected. For example, when first data read by the first read operation and second data read by the second read operation are determined to be different, the memory cell is refreshed.

公开(公告)号：US20180315463A1

公开(公告)日：2018-11-01

申请号：US15926672

申请日：2018-03-20

Applicant: Renesas Electronics Corporation

Inventor： Tomoya SAITO

IPC: G11C8/12 ,  G11C8/06 ,  G06F12/06 ,  G11C7/10

CPC classification number: G11C8/12 ,  G06F12/0646 ,  G06F21/73 ,  G06F21/79 ,  G06F2221/2105 ,  G09C1/00 ,  G11C7/1051 ,  G11C7/24 ,  G11C8/06 ,  G11C16/0425 ,  G11C16/22 ,  G11C2029/4402 ,  H04L9/0866

Abstract: A semiconductor device according to one embodiment includes a unique ID generation circuit configured to generate a unique ID using a memory array including a plurality of complementary cells, each of the complementary cells includes first and second memory cells MC1 and MC2. The unique ID generation circuit uses, when data in the complementary cell read out in a first state in which an initial threshold voltage of the first memory cell MC1 has been virtually offset and data in the complementary cell read out in a second state in which an initial threshold voltage of the second memory cell MC2 has been virtually offset coincide with each other, the data in the complementary cell as the unique ID.

公开(公告)号：US20190172837A1

公开(公告)日：2019-06-06

申请号：US16269797

申请日：2019-02-07

Applicant: Renesas Electronics Corporation

Inventor： Tomohiro YAMASHITA ,  Tamotsu OGATA ,  Masamichi FUJITO ,  Tomoya SAITO

IPC: H01L27/11573 ,  H01L27/11568 ,  H01L21/8238 ,  H01L49/02 ,  H01L21/28 ,  H01L29/423 ,  H01L27/1157 ,  H01L29/94 ,  H01L29/792 ,  H01L29/78 ,  H01L27/06 ,  H01L29/66

CPC classification number: H01L27/11573 ,  H01L21/823821 ,  H01L27/0629 ,  H01L27/11568 ,  H01L27/1157 ,  H01L28/87 ,  H01L28/90 ,  H01L28/91 ,  H01L29/40114 ,  H01L29/41791 ,  H01L29/42344 ,  H01L29/66181 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/7853 ,  H01L29/7855 ,  H01L29/792 ,  H01L29/94

Abstract: To downsize a semiconductor device that includes a non-volatile memory and a capacitive element on a semiconductor substrate. In a capacitive element region of a main surface of a semiconductor substrate, fins protruding from the main surface are arranged along the Y direction while extending in the X direction. In the capacitive element region of the main surface of the semiconductor substrate, capacitor electrodes of the capacitive elements are alternately arranged along the X direction while intersecting the fins. The fins are formed in a formation step of other fins which are arranged in a memory cell array of the non-volatile memory of the semiconductor substrate. One capacitor electrode is formed in a formation step of a control gate electrode of the non-volatile memory. Another capacitor electrode is formed in a formation step of a memory gate electrode of the non-volatile memory.

公开(公告)号：US20180067793A1

公开(公告)日：2018-03-08

申请号：US15650282

申请日：2017-07-14

Applicant: Renesas Electronics Corporation

Inventor： Tomoya SAITO ,  Masamichi FUJITO ,  Koichi ANDO ,  Takashi HASHIMOTO

IPC: G06F11/07

CPC classification number: G06F11/0727 ,  G06F11/073 ,  G06F11/0793 ,  G06F2212/72 ,  G11C16/28 ,  G11C16/3431 ,  G11C29/50004

Abstract: The present invention aims at providing a flash memory that can perform a refresh operation at an appropriate time before a read error occurs. The controller performs the first read operation in which the memory cell as the read target is made to draw out the potential of one of the bit lines, the bit line potential controller is made to draw out the potential of the other of the bit lines at the first speed, and concurrently, the sense amplifier is made to read data; the second read operation in which the memory cell as the read target is made to draw out the potential of one of the bit lines, the bit line potential controller is made to draw out the potential of the other of the bit lines at the second speed faster than the first speed, and concurrently, the sense amplifier is made to read data; and the refresh operation in which, when the data read by the first read operation and the data read by the second read operation are determined to be different, the data stored in the memory cell as the read target is rewritten.

公开(公告)号：US20240126472A1

公开(公告)日：2024-04-18

申请号：US18397851

申请日：2023-12-27

Applicant: Renesas Electronics Corporation

Inventor： Ken MATSUBARA ,  Takashi ITO ,  Takashi KURAFUJI ,  Yasuhiko TAITO ,  Tomoya SAITO ,  Akihiko KANDA

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0673

Abstract: A semiconductor device includes a logic circuit, a memory, and a storage device. The storage device has a first special information storage region into which special information is written before a solder reflow process, a second special information storage region into which special information for updating is written after the solder reflow process, and a data storage region. The first special information storage region is constituted by a memory cell having a high reflow resistance and in which data is retained even after the solder reflow process. The second special information storage region and the data storage region are constituted by memory cells having a low reflow resistance and in which data may not be retained during the solder reflow process.

公开(公告)号：US20180233202A1

公开(公告)日：2018-08-16

申请号：US15434346

申请日：2017-02-16

Applicant: Renesas Electronics Corporation

Inventor： Tomoya SAITO

IPC: G11C16/14 ,  H01L27/11568 ,  G11C16/26

CPC classification number: G11C16/14 ,  G11C16/0425 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/785 ,  H01L29/792

Abstract: A memory cell of a split gate type MONOS memory is formed over a plate-shaped fin being a part of a semiconductor substrate. In a data erase operation, in a selected memory cell on which erasing is performed, a drain region is applied with 0 V, a memory gate electrode is applied with a positive voltage, and accordingly, erasing is performed by the FN mechanism. Also, in the data erase operation, in an unselected memory cell on which the erasing is not performed, connected to the same memory gate line as the above-described selected memory cell, the drain region is in an open state, and the memory gate electrode is applied with the positive voltage, whereby an induced voltage region is generated in a channel region. Thus, a potential difference between the channel region and the memory gate electrode is small, and accordingly, the erasing is not performed.

公开(公告)号：US20230025357A1

公开(公告)日：2023-01-26

申请号：US17847967

申请日：2022-06-23

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Genta WATANABE ,  Ken MATSUBARA ,  Tomoya SAITO ,  Akihiko KANDA ,  Koichi TAKEDA ,  Takahiro SHIMOI

IPC: G11C11/16

Abstract: A semiconductor device capable of changing a data programming process in a simple manner according to a situation is provided. The semiconductor device includes a plurality of memory cells, a programming circuit for supplying a programming current to the memory cell, and a power supply circuit for supplying power to the programming circuit. The power supply circuit includes a charge pump circuit for boosting the external power supply, a voltage of the external power supply according to the selection indication, and a selectable circuit capable of switching the boosted voltage boosted by the charge pump circuit. The control circuit further includes a control circuit for executing data programming processing by the programming circuit by switching the selection indication.

公开(公告)号：US20220382483A1

公开(公告)日：2022-12-01

申请号：US17746437

申请日：2022-05-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Ken MATSUBARA ,  Takashi ITO ,  Takashi KURAFUJI ,  Yasuhiko TAITO ,  Tomoya SAITO ,  Akihiko KANDA

IPC: G06F3/06

Abstract: A semiconductor device includes a logic circuit, a memory, and a storage device. The storage device has a first special information storage region into which special information is written before a solder reflow process, a second special information storage region into which special information for updating is written after the solder reflow process, and a data storage region. The first special information storage region is constituted by a memory cell having a high reflow resistance and in which data is retained even after the solder reflow process. The second special information storage region and the data storage region are constituted by memory cells having a low reflow resistance and in which data may not be retained during the solder reflow process.

公开(公告)号：US20180315768A1

公开(公告)日：2018-11-01

申请号：US15904349

申请日：2018-02-24

Applicant: Renesas Electronics Corporation

Inventor： Tomohiro YAMASHITA ,  Tamotsu OGATA ,  Masamichi FUJITO ,  Tomoya SAITO

IPC: H01L27/11573 ,  H01L27/11568 ,  H01L49/02

CPC classification number: H01L27/11573 ,  H01L21/28273 ,  H01L21/823821 ,  H01L27/0629 ,  H01L27/11568 ,  H01L27/1157 ,  H01L28/87 ,  H01L28/90 ,  H01L28/91 ,  H01L29/41791 ,  H01L29/42344 ,  H01L29/66181 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/7853 ,  H01L29/7855 ,  H01L29/792 ,  H01L29/94

Abstract: To downsize a semiconductor device that includes a non-volatile memory and a capacitive element on a semiconductor substrate. In a capacitive element region of a main surface of a semiconductor substrate, fins protruding from the main surface are arranged along the Y direction while extending in the X direction. In the capacitive element region of the main surface of the semiconductor substrate, capacitor electrodes of the capacitive elements are alternately arranged along the X direction while intersecting the fins. The fins are formed in a formation step of other fins which are arranged in a memory cell array of the non-volatile memory of the semiconductor substrate. One capacitor electrode is formed in a formation step of a control gate electrode of the non-volatile memory. Another capacitor electrode is formed in a formation step of a memory gate electrode of the non-volatile memory.