公开(公告)号：US20190206789A1

公开(公告)日：2019-07-04

申请号：US16192521

申请日：2018-11-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Teruhiro KUWAJIMA ,  Yasutaka NAKASHIBA ,  Akira MATSUMOTO ,  Akio ONO ,  Tetsuya IIDA

IPC: H01L23/522 ,  H01L49/02 ,  H01L29/93 ,  H01L27/06 ,  H03L7/099

CPC classification number: H01L23/5223 ,  H01L27/0629 ,  H01L28/86 ,  H01L29/93 ,  H03L7/099

Abstract: A semiconductor device has a coil and wirings under the coil. In addition, a distance between the upper face of the wirings and the bottom face of the cod is 7 μm or larger, and the wirings have a plurality of linear wiring parts each wiring width of which is 1 μm or smaller. In addition, the linear wiring parts do not configure a loop wiring, and the coil and the linear wiring parts are overlapped with each other in planar view. Even if such wirings (linear wiring parts) are arranged under the coil, the characteristics (for example, RF characteristics) of the semiconductor device are not deteriorated. In addition, the area of the semiconductor device can be reduced or high integration of elements can be realized by laminating elements (for example, MOM capacitance elements and the like) having the coil and the linear wiring parts.

公开(公告)号：US20180277518A1

公开(公告)日：2018-09-27

申请号：US15861231

申请日：2018-01-03

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tetsuya IIDA ,  Yasutaka NAKASHIBA ,  Nobuya KOIKE

IPC: H01L25/065 ,  H01L23/528 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H01L23/31 ,  H01L23/544 ,  H01L25/00 ,  H01L21/78 ,  H01L21/56 ,  H01L21/02 ,  H01L23/495

CPC classification number: H01L25/0657 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/56 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/544 ,  H01L24/05 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83139 ,  H01L2224/8385 ,  H01L2224/92147 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06531 ,  H01L2225/06562 ,  H01L2225/06593 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An improvement is achieved in the reliability of a semiconductor device. A first semiconductor chip includes a semiconductor substrate, a wiring structure formed over the semiconductor substrate, an insulating film formed over the wiring structure, and a first insulating film formed over the insulating film. A second semiconductor chip includes a semiconductor substrate, a wiring structure formed over the semiconductor substrate, an insulating film formed over the wiring structure, and a second insulating film formed over the insulating film. The first insulating film forms an uppermost layer of the first semiconductor chip. The second insulating film forms an uppermost layer of the second semiconductor chip. Each of the first and second insulating films is made of a photosensitive resin film having an adhesive property. The first and second semiconductor chips are stacked such that the first insulating film of the first semiconductor chip and the second insulating film of the second semiconductor chip are in contact with each other.

公开(公告)号：US20180007298A1

公开(公告)日：2018-01-04

申请号：US15639231

申请日：2017-06-30

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tetsuya IIDA ,  Yasutaka NAKASHIBA

IPC: H04N5/378 ,  H04N5/376 ,  H04N5/341 ,  H04N5/3745

CPC classification number: H04N5/378 ,  H04N5/341 ,  H04N5/3745 ,  H04N5/3765

Abstract: To provide an imaging device capable of reducing the amount of data with a simple method. An imaging device includes: a plurality of sensor elements which is arranged in a matrix shape and each of which generates a photoelectric conversion voltage in accordance with an input light level; and a read circuit which is coupled to bit lines provided while being associated with respective columns of the sensor elements, and amplifies and reads the photoelectric conversion voltages generated in the sensor elements by being exposed at predetermined timing. The read circuit outputs differential data of the read photoelectric conversion voltages generated in the respective sensor elements that are adjacent to each other in the same row or column.

公开(公告)号：US20170229510A1

公开(公告)日：2017-08-10

申请号：US15372775

申请日：2016-12-08

Applicant: Renesas Electronics Corporation

Inventor： Tetsuya IIDA ,  Yasutaka NAKASHIBA

IPC: H01L27/146

CPC classification number: H01L27/14643 ,  H01L27/14607 ,  H01L27/1461 ,  H01L27/14614

Abstract: A solid-state image sensing device capable of suppressing a dark current and transfer failure during a global shutter operation is provided. The solid-state image sensing device according to one embodiment includes: a semiconductor substrate having a main surface and a back surface being on the opposite side of the main surface; a well region arranged in contact with the main surface in the semiconductor substrate; a photoelectric conversion region arranged in contact with the main surface in the well region; a charge holding region arranged in contact with the main surface in the well region; a floating diffusion region arranged in contact with the main surface in the well region; a first transfer gate so formed as to face the well region and the charge holding region; and a second transfer gate so formed as to face the well region.

公开(公告)号：US20210165160A1

公开(公告)日：2021-06-03

申请号：US16700580

申请日：2019-12-02

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tetsuya IIDA ,  Yasutaka NAKASHIBA ,  Seigo NAMIOKA ,  Tomoo NAKAYAMA

IPC: G02B6/122 ,  G02B6/13

Abstract: A semiconductor device includes a semiconductor substrate having a first surface, a second surface opposite to the first surface, and having a first recess portion formed on the first surface, a first cladding layer located in the first recess portion, and a first optical waveguide formed on the first cladding layer. The first optical waveguide overlaps with the first cladding layer in plan view.

公开(公告)号：US20200295530A1

公开(公告)日：2020-09-17

申请号：US16811959

申请日：2020-03-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tetsuya IIDA ,  Yasutaka NAKASHIBA

IPC: H01S5/026 ,  H01S5/10

Abstract: A semiconductor device includes a cladding layer and a first optical waveguide. The first optical waveguide is formed on the first cladding layer. An end surface of the first optical waveguide is inclined relative to a vertical line perpendicular to an upper surface of the cladding layer.

公开(公告)号：US20190317276A1

公开(公告)日：2019-10-17

申请号：US16370409

申请日：2019-03-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tetsuya IIDA ,  Yasutaka NAKASHIBA

IPC: G02B6/12 ,  H01L31/12 ,  H01L31/0232 ,  H01L31/02 ,  H01L31/18 ,  H01S5/022

Abstract: According to the present invention, a first semiconductor chip includes a semiconductor substrate, an optical waveguide formed on an upper surface of the semiconductor substrate, and a concave portion formed in the semiconductor substrate in a region that differs from a region in which the optical waveguide is formed. A second semiconductor chip includes a compound semiconductor substrate, and a light emitting unit formed on an upper surface of the compound semiconductor substrate and emitting a laser beam. The second semiconductor chip is mounted in the concave portion of the first semiconductor chip, and a pedestal which is an insulating film is formed between a bottom surface of the concave portion and a back surface of the compound semiconductor substrate.

公开(公告)号：US20180240905A1

公开(公告)日：2018-08-23

申请号：US15946060

申请日：2018-04-05

Applicant: Renesas Electronics Corporation

Inventor： Satoshi EGUCHI ,  Tetsuya IIDA ,  Akio ICHIMURA ,  Yuya ABIKO

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L21/265 ,  H01L29/423

CPC classification number: H01L29/7811 ,  H01L21/265 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/42372 ,  H01L29/66477 ,  H01L29/66712

Abstract: To provide a semiconductor device including a power semiconductor element having improved reliability. The semiconductor device has a cell region and a peripheral region formed outside the cell region. The n type impurity concentration of n type column regions in the cell region is made higher than that of n type column regions comprised of an epitaxial layer in the peripheral region. Further, a charge balance is kept in each of the cell region and the peripheral region and each total electric charge is set so that a total electric charge of first p type column regions and a total electric charge of n type column regions in the cell region become larger than a total electric charge of third p type column regions and n type column regions comprised of an epitaxial layer in the peripheral region, respectively.

公开(公告)号：US20220013457A1

公开(公告)日：2022-01-13

申请号：US16924968

申请日：2020-07-09

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tetsuya IIDA ,  Yasutaka NAKASHIBA ,  Shinichi UCHIDA

IPC: H01L23/522 ,  H01L49/02 ,  H03F3/04 ,  H03M1/12

Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor element, and a multilayer wiring. The semiconductor element is formed on the semiconductor substrate. The multilayer wiring includes a wiring electrically connected with the semiconductor element, and a first inductor. The multilayer wiring is formed on the semiconductor substrate such that the multilayer wiring covers the semiconductor element. The first inductor is formed such that the first inductor electrically isolated from the wiring and is magnetically connected with the wiring.

公开(公告)号：US20200161284A1

公开(公告)日：2020-05-21

申请号：US16598858

申请日：2019-10-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tetsuya IIDA ,  Yasutaka NAKASHIBA

IPC: H01L25/16 ,  H01L31/105 ,  H01L31/02 ,  H01L31/0232 ,  H01L23/373 ,  H01L23/00 ,  G02B6/42 ,  H04B10/40

Abstract: The semiconductor module includes a semiconductor chip and a semiconductor chip. The semiconductor chip includes an optical device such as an optical waveguide, an optical receiver, and a grating coupler, and a wiring formed over the optical device. The semiconductor chip includes a semiconductor element such as a MISFET formed in the semiconductor substrate, and a wiring formed over the semiconductor element. a top surface of the semiconductor chip is laminated to a top surface of the semiconductor chip such that the wirings are in direct contact with each other. In the semiconductor substrate, a through hole having a circular shape in plan view is formed, in the through hole, an insulating film is formed as a cladding layer, and the semiconductor substrate surrounded by the through hole constitutes an optical waveguide.