公开(公告)号：US20230291401A1

公开(公告)日：2023-09-14

申请号：US18059615

申请日：2022-11-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuhisa MORI ,  Toshiyuki HATA

IPC: H03K17/687 ,  H01L23/00 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/739 ,  H01L23/498

CPC classification number: H03K17/6871 ,  H01L23/49811 ,  H01L24/13 ,  H01L24/48 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/7397 ,  H01L29/7813 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/73265 ,  H01L2924/182 ,  H01L2924/1811 ,  H01L2924/13091

Abstract: Performance of a semiconductor device is enhanced. A loss of a circuit device using a semiconductor device as a switch is reduced. A semiconductor device includes: a first semiconductor chip having a first MOSFET of p-type and a first parasitic diode; and a second semiconductor chip having a second MOSFET of n-type and a second parasitic diode. On front surfaces of the first and second semiconductor chips, a first source electrode and a first gate wiring and a second source electrode and a second gate wiring are formed, respectively. On back surfaces of the first and second semiconductor chips, first and second drain electrodes are formed, respectively. The second back surface and the first front surface face each other such that the second drain electrode and the first source electrode come into contact with each other via a conductive paste.

公开(公告)号：US20130264696A1

公开(公告)日：2013-10-10

申请号：US13906771

申请日：2013-05-31

Applicant: Renesas Eastern Japan Semiconductor, Inc. ,  Renesas Electronics Corporation

Inventor： Ryoichi KAJIWARA ,  Masahiro KOIZUMI ,  Toshiaki MORITA ,  Kazuya TAKAHASHI ,  Munehisa KISHIMOTO ,  Shigeru ISHII ,  Toshinori HIRASHIMA ,  Yasushi TAKAHASHI ,  Toshiyuki HATA ,  Hiroshi SATO ,  Keiichi OOKAWA

IPC: H01L23/495

CPC classification number: H01L23/49555 ,  H01L21/4814 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L23/28 ,  H01L23/3107 ,  H01L23/495 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/81 ,  H01L24/83 ,  H01L24/84 ,  H01L24/97 ,  H01L29/7833 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/16245 ,  H01L2224/29011 ,  H01L2224/29015 ,  H01L2224/29101 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/40095 ,  H01L2224/40225 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/73253 ,  H01L2224/75251 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2224/83138 ,  H01L2224/83191 ,  H01L2224/83825 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/84801 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/10253 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H05K3/3426 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/01049 ,  H01L2924/01083 ,  H01L2224/29139 ,  H01L2924/3512 ,  H01L2224/48 ,  H01L2924/00012

Abstract: A semiconductor device featuring a semiconductor chip including a MOSFET and having a first main surface and a second, opposing main surface, a source electrode pad and a gate electrode pad over the first main surface, a drain electrode over the second main surface, a source external terminal and a gate external terminal, each having a first main surface electrically connected to the source electrode pad and gate electrode pad of the chip, respectively, and a drain external terminal having a first main surface and a second, opposing main surface and being electrically connected to the second main surface of the chip, each of the source, gate and drain external terminals having second main surfaces thereof in a same plane, and, in a plan view of the external terminals, the gate external terminal has a portion located between the source and drain external terminals in at least one direction.

Abstract translation: 一种半导体器件，其特征在于包括MOSFET的半导体芯片，具有第一主表面和第二主表面，第一主表面上的源极电极焊盘和栅电极焊盘，第二主表面上的漏电极，源极 外部端子和栅极外部端子，每个具有分别电连接到芯片的源电极焊盘和栅电极焊盘的第一主表面和具有第一主表面和第二相对主表面的漏极外部端子，并且是 电连接到芯片的第二主表面，源极，栅极和漏极外部端子中的每一个具有第二主表面在同一平面中，并且在外部端子的平面图中，栅极外部端子具有位于 在至少一个方向上在源极和漏极外部端子之间。

公开(公告)号：US20240063059A1

公开(公告)日：2024-02-22

申请号：US18142825

申请日：2023-05-03

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koichi ANDO ,  Toshiyuki HATA ,  Kosuke KITAICHI ,  Hiroi OKA

IPC: H01L21/784 ,  H01L29/06 ,  H01L29/66 ,  H01L21/66

CPC classification number: H01L21/784 ,  H01L29/0649 ,  H01L29/66712 ,  H01L22/30 ,  H01L22/12

Abstract: In a case where a crack occurs in a dicing step, the crack can be suppressed from proceeding toward an element region. A first scribe region and a second scribe region that both define an element region are formed in a main surface of a semiconductor wafer. In the first scribe region, an evaluation-deep-trench group including an evaluation-deep-trench-first portion and an evaluation-deep-trench-second portion is formed. The evaluation-deep-trench-first portion is formed in a first region. The evaluation-deep-trench-second portion has a width in an X-axis direction, and is formed in a bar shape extending in a Y-axis direction, in a second region located between the first region and the element region.

公开(公告)号：US20240006344A1

公开(公告)日：2024-01-04

申请号：US18330648

申请日：2023-06-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasutaka NAKASHIBA ,  Toshiyuki HATA ,  Hiroshi YANAGIGAWA ,  Tomohisa SEKIGUCHI

IPC: H01L23/00 ,  H01L23/58 ,  H01L29/78 ,  H01L21/78 ,  H01L21/306

CPC classification number: H01L23/562 ,  H01L24/32 ,  H01L23/585 ,  H01L29/7813 ,  H01L21/78 ,  H01L21/30604 ,  H01L2224/32225

Abstract: A semiconductor device includes a chip mounting portion and a semiconductor chip provided on the chip mounting portion via a conductive adhesive material. Here, a planar shape of the semiconductor chip is a quadrangular shape. Also, in plan view, a plurality of thin portions is formed at a plurality of corner portions of the semiconductor chip, respectively. Also, the plurality of thin portions respectively formed at the plurality of corner portions of the semiconductor chip is spaced apart from each other. Further, thickness of each of the plurality of thin portions is smaller than a thickness of the semiconductor chip other than the plurality of the thin portions.

公开(公告)号：US20230369178A1

公开(公告)日：2023-11-16

申请号：US18170159

申请日：2023-02-16

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Toshiyuki HATA

IPC: H01L23/495 ,  H01L23/00 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L23/49513 ,  H01L24/08 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L23/49816 ,  H01L2924/182 ,  H01L2224/08055 ,  H01L2224/08113 ,  H01L2224/32245 ,  H01L2224/48245 ,  H01L2224/4814 ,  H01L2224/4903

Abstract: A package construction includes: a die pad, and a suspension lead remaining portion connected to the die pad. Here, an offset portion is provided from a peripheral edge portion of the die pad to the suspension lead remaining portion. Also, the suspension lead remaining portion has: a first end portion connected to the die pad, and a second end portion opposite the first end portion. Further, the second end portion of the suspension lead remaining portion is exposed from the side surface of the sealing body at a position spaced apart from each of the upper surface and the lower surface.

公开(公告)号：US20130207252A1

公开(公告)日：2013-08-15

申请号：US13846730

申请日：2013-03-18

Applicant: Renesas Electronics Corporation

Inventor： Kuniharu MUTO ,  Toshiyuki HATA ,  Hiroshi SATO ,  Hiroi OKA ,  Osamu IKEDA

IPC: H01L23/495

CPC classification number: H01L23/49582 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/544 ,  H01L24/05 ,  H01L24/29 ,  H01L24/35 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/77 ,  H01L24/78 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L29/0615 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/37124 ,  H01L2224/40091 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/4103 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4846 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/4912 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/78 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84205 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85214 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01054 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/83205 ,  H01L2924/206

Abstract: To actualize a reduction in the on-resistance of a small surface mounted package having a power MOSFET sealed therein. A silicon chip is mounted on a die pad portion integrated with leads configuring a drain lead. The silicon chip has, on the main surface thereof, a source pad and a gate pad. The backside of the silicon chip configures a drain of a power MOSFET and bonded to the upper surface of a die pad portion via an Ag paste. A lead configuring a source lead is electrically coupled to the source pad via an Al ribbon, while a lead configuring a gate lead is electrically coupled to the gate pad via an Au wire.

Abstract translation: 实现密封在其中的功率MOSFET的小型表面安装封装的导通电阻的降低。 硅芯片安装在与构成漏极引线的引线集成的管芯焊盘部分上。 硅芯片在其主表面上具有源极焊盘和栅极焊盘。 硅芯片的背面配置功率MOSFET的漏极，并通过Ag浆料粘合到芯片焊盘部分的上表面。 构成源极引线的引线通过Al带电耦合到源极焊盘，而构成栅极引线的引线通过Au线电耦合到栅极焊盘。

公开(公告)号：US20230369278A1

公开(公告)日：2023-11-16

申请号：US17742975

申请日：2022-05-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasutaka NAKASHIBA ,  Toshiyuki HATA

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/16

CPC classification number: H01L24/33 ,  H01L23/3157 ,  H01L24/06 ,  H01L24/73 ,  H01L24/05 ,  H01L24/02 ,  H01L25/16 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05083 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/0615 ,  H01L2224/2919 ,  H01L2224/29139 ,  H01L2224/32245 ,  H01L2224/32145 ,  H01L2224/33181 ,  H01L2224/33505 ,  H01L24/45 ,  H01L2224/45144 ,  H01L2224/45124 ,  H01L24/46 ,  H01L2224/46 ,  H01L24/48 ,  H01L2224/48145 ,  H01L2224/48245 ,  H01L2224/49175 ,  H01L2224/49171 ,  H01L2224/49177 ,  H01L24/49 ,  H01L2224/73265 ,  H01L2224/73215 ,  H01L2224/0221 ,  H01L2224/02215 ,  H01L2924/13091 ,  H01L29/7813

Abstract: A semiconductor device includes: a first semiconductor chip mounted on a chip mounting portion via a first bonding material; and a second semiconductor chip mounted on the first semiconductor chip. Here, the first semiconductor chip has: a protective film located in an uppermost layer; and a first pad electrode exposed from the protective film at an inside of a first opening portion of the protective film. Also, the second semiconductor chip is mounted on a conductive material, which is arranged on the first pad electrode of the first semiconductor chip, via a second bonding material of an insulative property.

公开(公告)号：US20230352313A1

公开(公告)日：2023-11-02

申请号：US18170672

申请日：2023-02-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Toshiyuki HATA

IPC: H01L21/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/495 ,  H01L21/02

CPC classification number: H01L21/4821 ,  H01L21/76817 ,  H01L24/03 ,  H01L23/49503 ,  H01L21/02175 ,  H01L2021/60015

Abstract: In a frame member including a first region and a second region that are extending in a first direction in parallel to each other while being spaced apart from each other, first and second plating films are formed in the first and second regions, respectively. The second plating film is different in a type from the first plating film. Then, a stamping process is performed to the frame member including the first region and the second region, thereby a lead frame including a plurality of leads is formed. The lead frame includes a first lead group and a second lead group. The first plating film is formed in the first lead group, but the second plating film is not formed in the first lead group. Meanwhile, the second plating film is formed in the second lead group, but the first plating film is not formed in the second lead group.

公开(公告)号：US20230275069A1

公开(公告)日：2023-08-31

申请号：US18059583

申请日：2022-11-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroshi YANAGIGAWA ,  Yasutaka NAKASHIBA ,  Toshiyuki HATA

IPC: H01L25/065 ,  H01L23/495 ,  H01L23/498 ,  H01L23/482

CPC classification number: H01L25/0657 ,  H01L23/4828 ,  H01L23/49572 ,  H01L23/49844

Abstract: A semiconductor device includes a first semiconductor chip including a first MOSFET of n-type and a first parasitic diode and a second semiconductor chip including a second MOSFET of n-type and a second parasitic diode. A first source electrode and a first gate wiring are formed on a first front surface of the first semiconductor chip, and a first drain electrode is formed on a first back surface of the first semiconductor chip. A second source electrode and a second gate wiring are formed on a second front surface of the second semiconductor chip, and a second drain electrode is formed on a second back surface of the second semiconductor chip. The first back surface and the second back surface are faced to each other such that the first drain electrode and the second drain electrode are in contact with each other via a conductive tape.

公开(公告)号：US20220392865A1

公开(公告)日：2022-12-08

申请号：US17717756

申请日：2022-04-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Noriko OKUNISHI ,  Toshiyuki HATA

IPC: H01L23/00

Abstract: In order to reduce on-resistance in a semiconductor device to be used for high current applications, the semiconductor device includes a source terminal lead located between a gate terminal lead and a Kelvin terminal lead in plan view and electrically connected with a source terminal via a plurality of wires.