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公开(公告)号：US09847108B2
公开(公告)日：2017-12-19
申请号：US13675354
申请日：2012-11-13
Applicant: Renesas Electronics Corporation
Inventor： Muneaki Matsushige , Atsunori Hirobe , Kazutaka Kikuchi , Tetsuo Fukushi
Abstract: A semiconductor storage device includes: a plurality of memory cell arrays; a plurality of bidirectional data buses provided in correspondence with respective ones of the plurality of memory cell arrays; a plurality of bidirectional buffer circuits, which are provided in correspondence with respective ones of the memory cell arrays, capable of connecting adjacent bidirectional data buses serially so as to relay data in the bidirectional data buses; and a control circuit for controlling activation of the bidirectional buffer circuits. The bidirectional buffer circuit is arranged so as to invert logic and the bidirectional buffer circuit is arranged so as not to invert logic.
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公开(公告)号：US10714154B2
公开(公告)日：2020-07-14
申请号：US16794907
申请日：2020-02-19
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Hiroyuki Takahashi , Muneaki Matsushige
IPC: G11C5/14 , G11C7/06 , H01L27/108 , G11C11/409 , G11C7/08 , G11C11/4091 , G11C11/4074
Abstract: Even when a driven circuit has a large-scale load, a small-scale step-down driver circuit can supply an internal potential to the driven circuit at high speed. A semiconductor integrated circuit device includes a step-down driver circuit which supplies, to a driven circuit to be driven by an internal potential lower than an external potential supplied from an external power supply, the internal potential. The step-down driver circuit includes an NMOS transistor having a drain coupled to an external power supply terminal to be coupled to the external power supply and a source to be coupled to a voltage supply point of the driven circuit and a driver circuit to drive the gate of the NMOS transistor.
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公开(公告)号：US20160133301A1
公开(公告)日：2016-05-12
申请号：US14995067
申请日：2016-01-13
Applicant: Renesas Electronics Corporation
Inventor： Tetsuo Fukushi , Atsunori Hirobe , Muneaki Matsushige
CPC classification number: G11C5/147 , G11C5/025 , G11C5/063 , G11C8/12 , H01L23/481 , H01L23/49811 , H01L23/49822 , H01L23/50 , H01L24/16 , H01L24/17 , H01L25/0657 , H01L2224/13025 , H01L2224/14181 , H01L2224/16145 , H01L2224/16146 , H01L2224/16227 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/1434 , H01L2924/15311
Abstract: A semiconductor device includes a first semiconductor chip located over a substrate; and a second semiconductor chip located over the first semiconductor chip, wherein the first semiconductor chip includes a first internal power supply generation circuit that generates a first internal power supply voltage supplied to a first internal circuit; a first penetration electrode formed from an upper surface of the first semiconductor chip to an underside of the first semiconductor chip and electrically connected to the first internal power supply generation circuit; a first reference voltage generation circuit that generates a first reference voltage; and a second penetration electrode formed from the upper surface of the first semiconductor chip to the underside of the first semiconductor chip and electrically connected to the first reference voltage generation circuit.
Abstract translation: 半导体器件包括位于衬底上的第一半导体芯片; 以及位于所述第一半导体芯片上方的第二半导体芯片，其中所述第一半导体芯片包括产生提供给第一内部电路的第一内部电源电压的第一内部电源产生电路; 第一穿透电极，由第一半导体芯片的上表面形成到第一半导体芯片的下侧，并电连接到第一内部电源产生电路; 产生第一参考电压的第一参考电压产生电路; 以及第二穿透电极，其从所述第一半导体芯片的上表面形成到所述第一半导体芯片的下侧，并且电连接到所述第一参考电压产生电路。
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公开(公告)号：US09251886B2
公开(公告)日：2016-02-02
申请号：US14807957
申请日：2015-07-24
Applicant: Renesas Electronics Corporation
Inventor： Tetsuo Fukushi , Atsunori Hirobe , Toshikatsu Jinbo , Muneaki Matsushige
IPC: G11C5/02 , G11C11/4091 , G11C7/14 , G11C11/4097
CPC classification number: G11C5/025 , G11C5/02 , G11C5/14 , G11C7/06 , G11C7/14 , G11C11/4091 , G11C11/4097
Abstract: A semiconductor storage device 1 according to an aspect includes a first memory area 11—1 and a second memory area 11—2. Memory cells MC_m_n and bit lines BL1, BL2_, . . . , BLm— are disposed in a boundary area 18 between the first and second memory areas 11—1 and 11—2. The memory cells MC_m_n disposed in the boundary area 18 includes memory cells into which no data is written, and a line 56 is formed in a place that overlaps memory cells disposed in the boundary area 18 when the boundary area 18 is viewed from the top. As a result, it is possible to increase the integration density of a memory cell array and provide a line in the memory cell array.
Abstract translation: 根据本发明的半导体存储装置1包括第一存储区域11-1和第二存储区域11-2。 存储单元MC_m_n和位线BL1，BL2_，。 。 。 BLm-设置在第一和第二存储区域11-1和11-2之间的边界区域18中。 设置在边界区域18中的存储单元MC_m_n包括其中没有写入数据的存储单元，并且当从顶部观看边界区域18时，在与边界区域18中重叠的存储单元重叠的位置处形成行56。 结果，可以增加存储单元阵列的集成密度并在存储单元阵列中提供一行。
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公开(公告)号：US09123391B2
公开(公告)日：2015-09-01
申请号：US14082320
申请日：2013-11-18
Applicant: Renesas Electronics Corporation
Inventor： Tetsuo Fukushi , Atsunori Hirobe , Toshikatsu Jinbo , Muneaki Matsushige
IPC: G11C5/02 , G11C11/4097 , G11C7/14
CPC classification number: G11C5/025 , G11C5/02 , G11C5/14 , G11C7/06 , G11C7/14 , G11C11/4091 , G11C11/4097
Abstract: A semiconductor storage device 1 according to an aspect includes a first memory area 11—1 and a second memory area 11—2. Memory cells MC_m_n and bit lines BL1, BL2_, . . . . , BLm_are disposed in a boundary area 18 between the first and second memory areas 11—1 and 11—2. The memory cells MC_m_n disposed in the boundary area 18 includes memory cells into which no data is written, and a line 56 is formed in a place that overlaps memory cells disposed in the boundary area 18 when the boundary area 18 is viewed from the top. As a result, it is possible to increase the integration density of a memory cell array and provide a line in the memory cell array.
Abstract translation: 根据本发明的半导体存储装置1包括第一存储区域11-1和第二存储区域11-2。 存储单元MC_m_n和位线BL1，BL2_，。 。 。 。 BLm_被布置在第一和第二存储区域11-1和11-2之间的边界区域18中。 设置在边界区域18中的存储单元MC_m_n包括其中没有写入数据的存储单元，并且当从顶部观看边界区域18时，在与边界区域18中重叠的存储单元重叠的位置处形成行56。 结果，可以增加存储单元阵列的集成密度并在存储单元阵列中提供一行。
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Patent Agency Ranking
公开(公告)号：US10607663B2
公开(公告)日：2020-03-31
申请号：US15914822
申请日：2018-03-07
Applicant: Renesas Electronics Corporation
Inventor： Hiroyuki Takahashi , Muneaki Matsushige
IPC: G11C5/14 , G11C7/06 , H01L27/108 , G11C11/409 , G11C11/4074 , G11C11/4091 , G11C7/08
Abstract: Even when a driven circuit has a large-scale load, a small-scale step-down driver circuit can supply an internal potential to the driven circuit at high speed. A semiconductor integrated circuit device includes a step-down driver circuit which supplies, to a driven circuit to be driven by an internal potential lower than an external potential supplied from an external power supply, the internal potential. The step-down driver circuit includes an NMOS transistor having a drain coupled to an external power supply terminal to be coupled to the external power supply and a source to be coupled to a voltage supply point of the driven circuit and a driver circuit to drive the gate of the NMOS transistor.
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公开(公告)号：US09251868B2
公开(公告)日：2016-02-02
申请号：US14676735
申请日：2015-04-01
Applicant: Renesas Electronics Corporation
Inventor： Tetsuo Fukushi , Atsunori Hirobe , Muneaki Matsushige
CPC classification number: G11C5/147 , G11C5/025 , G11C5/063 , G11C8/12 , H01L23/481 , H01L23/49811 , H01L23/49822 , H01L23/50 , H01L24/16 , H01L24/17 , H01L25/0657 , H01L2224/13025 , H01L2224/14181 , H01L2224/16145 , H01L2224/16146 , H01L2224/16227 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/1434 , H01L2924/15311
Abstract: An object of the invention is to make effective use of the structure of a multilayered semiconductor device that uses penetration electrodes in such a manner that the layered chips obtain stable internal power supply voltages with no increase in current consumption or in the area of the layered chips. Internal power supply generation circuits furnished in each of the layered core chips have their outputs commonly coupled via electrodes penetrating the layered core chips. This allows electrical charges to be shared among the core chips, optimizes internal power consumption of the multilayered semiconductor device as a whole, and inhibits fluctuations in the internal power supply voltages.
Abstract translation: 本发明的目的是有效地利用使用穿透电极的多层半导体器件的结构，使得分层芯片获得稳定的内部电源电压而不增加电流消耗或者在分层芯片的区域 。 在每个分层核心芯片中提供的内部电源产生电路的输出通常通过穿透分层芯片的电极耦合。 这允许在核心芯片之间共享电荷，从而整体上优化多层半导体器件的内部功耗，并且抑制内部电源电压的波动。
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公开(公告)号：US11710511B2
公开(公告)日：2023-07-25
申请号：US17501411
申请日：2021-10-14
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Tetsuo Fukushi , Hiroyuki Takahashi , Muneaki Matsushige
Abstract: A semiconductor device includes a memory mat having: a plurality of memory cells; a sense amplifier connected to a memory cell selected from the plurality of memory cells; a first power supply wiring; a first switch connected between the sense amplifier and the first power supply wiring and made an ON state in operating the sense amplifier; and a second switch connected to the sense amplifier and made an ON state in operating the sense amplifier, a second power supply wiring arranged outside the memory mat and connected to the first power supply wiring, a third power supply wiring arranged outside the memory mat and connected to the sense amplifier via the second switch, and a short switch arranged outside the memory mat and connected between the second and third power supply wirings. Here, in operating the sense amplifier, the short switch is made an ON state.
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公开(公告)号：US09384788B2
公开(公告)日：2016-07-05
申请号：US14995067
申请日：2016-01-13
Applicant: Renesas Electronics Corporation
Inventor： Tetsuo Fukushi , Atsunori Hirobe , Muneaki Matsushige
CPC classification number: G11C5/147 , G11C5/025 , G11C5/063 , G11C8/12 , H01L23/481 , H01L23/49811 , H01L23/49822 , H01L23/50 , H01L24/16 , H01L24/17 , H01L25/0657 , H01L2224/13025 , H01L2224/14181 , H01L2224/16145 , H01L2224/16146 , H01L2224/16227 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/1434 , H01L2924/15311
Abstract: A semiconductor device includes a first semiconductor chip located over a substrate; and a second semiconductor chip located over the first semiconductor chip, wherein the first semiconductor chip includes a first internal power supply generation circuit that generates a first internal power supply voltage supplied to a first internal circuit; a first penetration electrode formed from an upper surface of the first semiconductor chip to an underside of the first semiconductor chip and electrically connected to the first internal power supply generation circuit; a first reference voltage generation circuit that generates a first reference voltage; and a second penetration electrode formed from the upper surface of the first semiconductor chip to the underside of the first semiconductor chip and electrically connected to the first reference voltage generation circuit.
Abstract translation: 半导体器件包括位于衬底上的第一半导体芯片; 以及位于所述第一半导体芯片上方的第二半导体芯片，其中所述第一半导体芯片包括产生提供给第一内部电路的第一内部电源电压的第一内部电源产生电路; 第一穿透电极，由第一半导体芯片的上表面形成到第一半导体芯片的下侧，并电连接到第一内部电源产生电路; 产生第一参考电压的第一参考电压产生电路; 以及第二穿透电极，其从所述第一半导体芯片的上表面形成到所述第一半导体芯片的下侧，并且电连接到所述第一参考电压产生电路。
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公开(公告)号：US20150287441A1
公开(公告)日：2015-10-08
申请号：US14676735
申请日：2015-04-01
Applicant: Renesas Electronics Corporation
Inventor： Tetsuo FUKUSHI , Atsunori Hirobe , Muneaki Matsushige
CPC classification number: G11C5/147 , G11C5/025 , G11C5/063 , G11C8/12 , H01L23/481 , H01L23/49811 , H01L23/49822 , H01L23/50 , H01L24/16 , H01L24/17 , H01L25/0657 , H01L2224/13025 , H01L2224/14181 , H01L2224/16145 , H01L2224/16146 , H01L2224/16227 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/1434 , H01L2924/15311
Abstract: An object of the invention is to make effective use of the structure of a multilayered semiconductor device that uses penetration electrodes in such a manner that the layered chips obtain stable internal power supply voltages with no increase in current consumption or in the area of the layered chips. Internal power supply generation circuits furnished in each of the layered core chips have their outputs commonly coupled via electrodes penetrating the layered core chips. This allows electrical charges to be shared among the core chips, optimizes internal power consumption of the multilayered semiconductor device as a whole, and inhibits fluctuations in the internal power supply voltages.
Abstract translation: 本发明的目的是有效地利用使用穿透电极的多层半导体器件的结构，使得分层芯片获得稳定的内部电源电压而不增加电流消耗或者在分层芯片的区域 。 在每个分层核心芯片中提供的内部电源产生电路的输出通常通过穿透分层芯片的电极耦合。 这允许在核心芯片之间共享电荷，从而整体上优化多层半导体器件的内部功耗，并且抑制内部电源电压的波动。
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