公开(公告)号：US10255956B2

公开(公告)日：2019-04-09

申请号：US15845698

申请日：2017-12-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takashi Iwase ,  Ken Matsubara

IPC: G11C7/00 ,  G11C7/12 ,  G11C7/14 ,  G11C7/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  G11C16/32 ,  G11C16/26

Abstract: According to an embodiment, a semiconductor device includes a pre-charge transistor configured to supply a pre-charge voltage to a bit line, a sense amplifier configured to change a logic level of an output signal according to a result of a comparison between a drawing current of a storage element and a reference current, a clamp transistor disposed between the bit line BL and the sense amplifier, and a clamp voltage output transistor, in which a gate of the clamp voltage output transistor is connected to a gate of the clamp transistor, a source of the clamp voltage output transistor is connected to a back gate thereof, the pre-charge voltage is supplied to the source of the clamp voltage output transistor, a drain of the clamp voltage output transistor is connected to the gate thereof, and a ground voltage is supplied to a back gate of the clamp transistor.

公开(公告)号：US20170351312A1

公开(公告)日：2017-12-07

申请号：US15482187

申请日：2017-04-07

Applicant: Renesas Electronics Corporation

Inventor： Takashi Iwase ,  Ken Matsubara ,  Hidenori Mitani ,  Hiroshi Sato

IPC: G06F1/30 ,  G06F1/26 ,  G06F11/14

CPC classification number: G06F1/30 ,  G06F1/263 ,  G06F11/1441 ,  G06F2201/84

Abstract: There is to provide a semiconductor device capable of storing save data at a shutdown of a power. The semiconductor device of receiving the power includes a memory unit having a plurality of memory cells capable of storing data, a power detecting circuit that detects shutdown of the power, and a condenser capable of temporarily supplying an operation voltage, instead of the power, at the power shutdown. The memory unit includes a voltage generating unit that generates a plurality of writing voltages based on the operation voltage from the condenser at the power shutdown and a writing circuit that performs data writing of save data for a plurality of memory cells, based on the writing voltages generated by the voltage generating unit.

公开(公告)号：US10665271B2

公开(公告)日：2020-05-26

申请号：US16151089

申请日：2018-10-03

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koichi Takeda ,  Takashi Iwase

IPC: G11C5/14 ,  H03K19/0185 ,  G11C7/10 ,  G11C8/08 ,  G11C8/14 ,  G11C8/18 ,  H03K5/1534 ,  G11C8/10

Abstract: According to an embodiment, a word line driver includes: a first inverter that is driven by a first power supply voltage and inverts and outputs a decode signal; a second inverter that is driven by a second power supply voltage and inverts and outputs the decode signal; a first PMOS transistor that is controlled to be turned on or off on the basis of an output signal of the second inverter; a first NMOS transistor that is controlled to be turned on or off on the basis of an output signal of the first inverter; and a second PMOS transistor that is provided between a power supply voltage terminal to which the second power supply voltage is supplied and the gate of the first PMOS transistor and is temporarily turned on in synchronization with falling of the decode signal.

公开(公告)号：US10192621B2

公开(公告)日：2019-01-29

申请号：US15915823

申请日：2018-03-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Ken Matsubara ,  Takashi Iwase ,  Satoru Nakanishi

IPC: G11C11/34 ,  G11C16/08 ,  G11C16/04 ,  H03K3/356

Abstract: In order to reduce the manufacturing cost, a flash memory includes a memory cell array formed by a plurality of memory cells arranged in a matrix shape; a plurality of word lines provided in each column of the memory cell array; a first word line driver that outputs a first voltage group to each of the word lines; and a second word line driver that outputs a second voltage group to each of the word lines together with the first word line driver.

公开(公告)号：US09947409B2

公开(公告)日：2018-04-17

申请号：US15432228

申请日：2017-02-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Ken Matsubara ,  Takashi Iwase ,  Satoru Nakanishi

IPC: G11C11/34 ,  G11C16/08 ,  G11C16/04 ,  H03K3/356

CPC classification number: G11C16/08 ,  G11C16/0416 ,  G11C16/0433 ,  H03K3/356104

Abstract: In order to reduce the manufacturing cost, a flash memory includes a memory cell array formed by a plurality of memory cells arranged in a matrix shape; a plurality of word lines provided in each column of the memory cell array; a first word line driver that outputs a first voltage group to each of the word lines; and a second word line driver that outputs a second voltage group to each of the word lines together with the first word line driver.