公开(公告)号：US09797950B2

公开(公告)日：2017-10-24

申请号：US15007246

申请日：2016-01-27

Applicant: Renesas Electronics Corporation

Inventor： Takuro Nishikawa

IPC: G01R31/3185

CPC classification number: G01R31/318536 ,  G01R31/318544 ,  G01R31/318547 ,  G01R31/318555 ,  G01R31/318563 ,  G01R31/318566 ,  G01R31/318569 ,  G01R31/318575

Abstract: A semiconductor device addresses to a problem in which a current consumption variation rate increases during BIST execution causing resonance noise generation in a power supply line. The semiconductor device includes a self-diagnosis control circuit, a scan target circuit including a combinational circuit and a scan flip-flop, and an electrically rewritable non-volatile memory. A scan chain is configured by coupling a plurality of the scan flip-flops. In accordance with parameters stored in the non-volatile memory, the self-diagnosis control circuit can change a length of at least one of a scan-in period, a scan-out period and a capture period, and can also change a scan start timing.

公开(公告)号：US11214297B2

公开(公告)日：2022-01-04

申请号：US15948004

申请日：2018-04-09

Applicant: Renesas Electronics Corporation

Inventor： Takuro Nishikawa ,  Takao Koike ,  Shinya Abe

IPC: H02H7/08 ,  B62D5/04 ,  H02M7/5395 ,  H02P29/032 ,  H03M1/64 ,  H02P27/06

Abstract: A motor control system includes a first MCU and a second MCU. The first MCU includes an error detection unit, a resolver digital converter, and a first PWM generation unit. The resolver digital converter includes an encoder unit, which generates encoder pulses based on angle information and outputs the encoder pulses to the second MCU. The error detection unit outputs an error signal to the second MCU, when an error is detected in the first MCU. The first MCU controls the resolver digital converter to operate using a backup clock supplied from the second MCU.

公开(公告)号：US11677829B2

公开(公告)日：2023-06-13

申请号：US17173571

申请日：2021-02-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takuro Nishikawa

IPC: G06F15/16 ,  H04L67/12 ,  H04L12/40 ,  H04L49/90

CPC classification number: H04L67/12 ,  H04L12/40013 ,  H04L12/40202 ,  H04L49/9042 ,  H04L2012/40215

Abstract: A data processing device includes a first CPU (Central Processing Unit), a first memory, a CAN (Controller Area Network) controller and a system bus coupled to the first CPU, the first memory and the CAN controller, wherein the CAN controller comprises a receive buffer that stores a plurality of messages each of which has a different ID, and a DMA (Direct Memory Access) controller that selects the latest message among messages having a fist ID stored in the receive buffer and transfers the selected latest message to the first memory, wherein the message is one of CAN, CAN FD and CAN XL messages.

公开(公告)号：US10915082B2

公开(公告)日：2021-02-09

申请号：US16048282

申请日：2018-07-29

Applicant: Renesas Electronics Corporation

Inventor： Takuro Nishikawa ,  Masaki Fujigaya

IPC: G06F11/18 ,  G05B19/042 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3234 ,  G06F11/16 ,  G06F11/36 ,  G06F1/20 ,  G06F1/3293

Abstract: To provide a microcontroller that suppresses increase of power consumption during debugging, a microcontroller according to the present invention includes a first signal processing circuit, a second signal processing circuit that performs signal processing in the same manner as the first signal processing circuit, a comparing circuit that compares a processing result of the first signal processing circuit and a processing result of the second signal processing circuit with each other, and outputs an error signal when an error is detected, a suppressing signal input unit that receives a suppressing signal for suppressing an operation of the second signal processing circuit and an operation of the comparing circuit, a suppressing circuit that receives the suppressing signal from the suppressing signal input unit and suppresses the operation of the second signal processing circuit and the operation of the comparing circuit, and a pseudo error signal output circuit that outputs a pseudo error signal in place of the error signal, when the operation of the second signal processing circuit and the operation of the comparing circuit are suppressed.

公开(公告)号：US12174691B2

公开(公告)日：2024-12-24

申请号：US18061776

申请日：2022-12-05

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takuro Nishikawa

IPC: G06F11/00 ,  G06F11/07

Abstract: The semiconductor device 10 receives an input signal given from the signal generating unit provided externally by a plurality of receiving units, a receiving unit 12, 13 for generating a plurality of received signals from the received input signal, a plurality of received signals by comparing, an error determination unit 14 for outputting an error notification to the upper system in response to the error between the channels that occurs between the received signals becomes equal to or greater than the threshold value, the threshold count value is stored and a threshold count register 17, the error determination unit 14 waits for the departure of the error notification until the period specified by the threshold count value has elapsed.

公开(公告)号：US10317466B2

公开(公告)日：2019-06-11

申请号：US15707532

申请日：2017-09-18

Applicant: Renesas Electronics Corporation

Inventor： Takuro Nishikawa

IPC: G01R31/3185

Abstract: A semiconductor device addresses to a problem in which a current consumption variation rate increases during BIST execution causing resonance noise generation in a power supply line. The semiconductor device includes a self-diagnosis control circuit, a scan target circuit including a combinational circuit and a scan flip-flop, and an electrically rewritable non-volatile memory. A scan chain is configured by coupling a plurality of the scan flip-flops. In accordance with parameters stored in the non-volatile memory, the self-diagnosis control circuit can change a length of at least one of a scan-in period, a scan-out period and a capture period, and can also change a scan start timing.

公开(公告)号：US10230495B2

公开(公告)日：2019-03-12

申请号：US15622701

申请日：2017-06-14

Applicant: Renesas Electronics Corporation

Inventor： Takuro Nishikawa

IPC: G06F11/10 ,  H03M13/00 ,  H04L1/00 ,  H03M13/15 ,  H04B1/40 ,  H03M13/09

Abstract: Provided is a CRC calculation circuit capable of dealing with various types of generator polynomials with a simple configuration. A CRC calculation circuit (100) includes a generator polynomial register (110) configured to store polynomial data, and a plurality of CRC calculation units (120) connected in series and provided so as to correspond to the number of bits of input data. The CRC calculation units (120) each include a barrel shifter (121) configured to shift calculated data by one bit using the input data or output data from a pre-stage CRC calculation unit as the calculated data; an XOR circuit (122) configured to perform XOR calculation of the shifted data and the polynomial data; and a multiplexer (123) configured to select, based on the calculated data, the shifted data or calculation result data.

公开(公告)号：US09632568B2

公开(公告)日：2017-04-25

申请号：US13742442

申请日：2013-01-16

Applicant: Renesas Electronics Corporation

Inventor： Takuro Nishikawa

IPC: G06F1/32 ,  G06F1/26 ,  G06F1/00

CPC classification number: G06F1/3296 ,  G06F1/3287 ,  Y02D10/171

Abstract: Disclosed as one aspect is a semiconductor device including a transmission/reception interface that is used for transmission and reception of data, a processing unit that processes the data, a monitoring unit that monitors received data and detects a specific frame allowed to be transmitted regardless of a state of a circuit to transmit/receive the data, and a power management unit that controls power consumption of a circuit including the processing unit.