公开(公告)号：US20230087101A1

公开(公告)日：2023-03-23

申请号：US17886033

申请日：2022-08-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoichi IIZUKA ,  Fukashi MORISHITA

IPC: H03M1/36 ,  H03K23/54 ,  H03M1/08 ,  H03M1/50 ,  H03K23/44

Abstract: An integrating Analog-to-digital converter has a global counter that outputs a counter code signal including a multiphase signal. It also has a column circuit including: a ramp wave generation circuit outputting a ramp wave voltage; a comparator comparing the ramp wave voltage with a pixel voltage; and a latch circuit latching the counter code signal at output inversion timing of the comparator. An output value of the latch circuit is used as a digital conversion output value per the column circuit. The counter has a phase division circuit outputting, as an LSB of the digital conversion output value of the integrating analog-to-digital converter, a phase division signal to the latch circuit, the phase division signal dividing a phase of the counter code signal. The phase division circuit is arranged to a plurality of column circuits, and the LSB is shared by a plurality of phase division circuits.

公开(公告)号：US20150055398A1

公开(公告)日：2015-02-26

申请号：US14537452

申请日：2014-11-10

Applicant: Renesas Electronics Corporation

Inventor： Masayasu KOMYO ,  Yoichi IIZUKA

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C11/4093 ,  G06F13/4072 ,  G06F2213/0038 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/22 ,  G11C11/4096 ,  H03K19/0005 ,  Y02D10/14 ,  Y02D10/151

Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit that transmits data in parallel through a plurality of signal lines and a data receiving circuit that receives the data. The data transmitting circuit includes a plurality of data output circuits that output the data in a data transmission mode or set an output to a high impedance state in a HiZ mode, a plurality of data selection circuits that select one of the data and fixed data and output the selected data to the data output circuits, and a control circuit that controls the data output circuits to output the fixed data during a period between a time when a mode is switched from the HiZ mode to the data transmission mode and a time when the data output circuits start to output the data.

Abstract translation: 提供了根据本发明的示例性方面的半导体集成电路，其包括通过多条信号线并行发送数据的数据发送电路和接收数据的数据接收电路。 数据发送电路包括多个数据输出电路，其以数据传输模式输出数据或将输出设置为HiZ模式中的高阻抗状态;多个数据选择电路，选择数据和固定数据之一;以及 将选择的数据输出到数据输出电路，以及控制电路，其控制数据输出电路在模式从HiZ模式切换到数据传输模式的时间段期间输出固定数据，以及时间 数据输出电路开始输出数据。

公开(公告)号：US20230412947A1

公开(公告)日：2023-12-21

申请号：US18319152

申请日：2023-05-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoichi IIZUKA ,  Fukashi MORISHITA

IPC: H04N25/772

CPC classification number: H04N25/772

Abstract: A solid-state image sensor includes a buffer circuit, and an AD conversion circuit. The buffer circuit is connected to a first pixel and a second pixel of a plurality of pixels. The AD conversion circuit converts a voltage signal from the buffer circuit into a digital signal. The buffer circuit includes a voltage holding circuit connected to the first pixel, a voltage holding circuit connected to the second pixel, and a switch circuit. The switch circuit selectively switches the voltage holding circuit which outputs a voltage signal to the AD conversion circuit between the voltage holding circuits. The buffer circuit carries out an operation of holding a voltage signal of the first pixel in the voltage holding circuit and an operation of holding a voltage signal of the second pixel in the voltage holding circuit in parallel with each other.

公开(公告)号：US20140119142A1

公开(公告)日：2014-05-01

申请号：US14148135

申请日：2014-01-06

Applicant: Renesas Electronics Corporation

Inventor： Masayasu KOMYO ,  Yoichi IIZUKA

IPC: G11C11/4096

CPC classification number: G11C11/4093 ,  G06F13/4072 ,  G06F2213/0038 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/22 ,  G11C11/4096 ,  H03K19/0005 ,  Y02D10/14 ,  Y02D10/151

Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit that transmits data in parallel through a plurality of signal lines and a data receiving circuit that receives the data. The data transmitting circuit includes a plurality of data output circuits that output the data in a data transmission mode or set an output to a high impedance state in a HiZ mode, a plurality of data selection circuits that select one of the data and fixed data and output the selected data to the data output circuits, and a control circuit that controls the data output circuits to output the fixed data during a period between a time when a mode is switched from the HiZ mode to the data transmission mode and a time when the data output circuits start to output the data.

Abstract translation: 提供了根据本发明的示例性方面的半导体集成电路，其包括通过多个信号线并行发送数据的数据发送电路和接收数据的数据接收电路。 数据发送电路包括多个数据输出电路，其以数据传输模式输出数据或将输出设置为HiZ模式中的高阻抗状态;多个数据选择电路，选择数据和固定数据之一;以及 将选择的数据输出到数据输出电路，以及控制电路，其控制数据输出电路在模式从HiZ模式切换到数据传输模式的时间段期间输出固定数据，以及时间 数据输出电路开始输出数据。