公开(公告)号：US20210026788A1

公开(公告)日：2021-01-28

申请号：US17066998

申请日：2020-10-09

Applicant: Renesas Electronics Corporation

Inventor： Sho YAMANAKA ,  Toshiyuki HIRAKI ,  Yoshihiko HOTTA ,  Takahiro IRITA

IPC: G06F13/16 ,  G06F13/362 ,  G06F13/40 ,  G11C11/406

Abstract: A semiconductor device includes a first master and a second master configured to issue requests for accessing to a memory, a first request issuing controller coupled to the first master, and configured to hold the request issued from the first master, a second request issuing controller coupled to the second master, and configured to hold the request issued from the second master, a bus arbiter coupled to the first request issuing controller and the second request issuing controller, a memory controller coupled to the bus arbiter, and including a buffer configured to store the requests issued from the first master and the second master, and a central bus controller configured to grant access rights to the first request issuing controller and the second request issuing controller based on space information of the buffer.

公开(公告)号：US20210141749A1

公开(公告)日：2021-05-13

申请号：US17150565

申请日：2021-01-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Katsuya MIZUMOTO ,  Toshiyuki HIRAKI ,  Nobuhiko HONDA ,  Sho YAMANAKA ,  Takahiro IRITA ,  Yoshihiko HOTTA

IPC: G06F13/16 ,  G06F13/362 ,  G06F13/18

Abstract: Access control is achieved in consideration of write training. Masters issue access requests including a read request and a write request. A memory controller accesses memory in response to the access requests issued by the maters. A central bus-control system controls the output of the access requests issued by the masters to the memory controller. A training circuit conducts training on the memory while the access to the memory is stopped. The central bus-control system further controls the execution of the training on the memory. During the training, the central bus-control system suppresses the output of the read request to the memory controller from among the access requests issued by the masters.

公开(公告)号：US20130073765A1

公开(公告)日：2013-03-21

申请号：US13674043

申请日：2012-11-11

Applicant: Renesas Electronics Corporation

Inventor： Yoshihiko HOTTA ,  Seiichi SAITO ,  Hiroyuki HAMASAKI ,  Hirotaka HARA ,  Itaru NONOMURA

IPC: G06F13/24

CPC classification number: G06F1/3253 ,  G06F1/3237 ,  Y02D10/128 ,  Y02D10/151

Abstract: In a data processor having a bus controller that performs timing control of access from the CPU operated in synchronization with a high-speed first clock signal to a peripheral circuit operated in synchronization with a low-speed second clock signal, a timing control circuit is provided between the peripheral circuit and the bus controller, and the bus controller causes, in response to a read instruction from the peripheral circuit, the timing control circuit to output data held by the peripheral circuit to the bus controller in synchronization with the cycle of the high-speed clock signal, causes the timing control circuit to start, in response to a write instruction directed to the peripheral circuit, writing into the peripheral circuit in synchronization with the cycle of the high-speed clock signal, and terminates the writing in synchronization with the cycle of the low-speed clock signal.

Abstract translation: 在具有总线控制器的数据处理器中，总线控制器执行与高速第一时钟信号同步操作的CPU的访问定时控制到与低速第二时钟信号同步操作的外围电路，提供定时控制电路 在外围电路和总线控制器之间，并且总线控制器响应于来自外围电路的读取指令而导致定时控制电路将周边电路保持的数据与高速的周期同步地传送到总线控制器 速度时钟信号，使定时控制电路响应于指向外围电路的写指令而启动，与高速时钟信号的周期同步地写入外围电路，并且与 低速时钟信号的周期。

公开(公告)号：US20170270063A1

公开(公告)日：2017-09-21

申请号：US15127765

申请日：2015-10-01

Applicant: Renesas Electronics Corporation

Inventor： Sho YAMANAKA ,  Toshiyuki HIRAKI ,  Yoshihiko HOTTA ,  Takahiro IRITA

IPC: G06F13/16 ,  G11C11/406 ,  G06F13/40

CPC classification number: G06F13/1673 ,  G06F13/1605 ,  G06F13/362 ,  G06F13/4068 ,  G11C11/406

Abstract: A semiconductor device according to the present invention includes a plurality of masters (100), a memory controller (400a), a bus that connects the plurality of masters (100) and the memory controller (400a), a QoS information register (610) that stores QoS information of the plurality of masters (100), a right grant number controller (602) that calculates the number of grantable access rights based on space information of a buffer (401) of the memory controller (400a), a right grant selection controller (603a) that selects the master (100) which will be granted the access right based on the QoS information of the QoS information register (610) and the number of grantable rights from the right grant number controller (602), and a request issuing controller (201a) that does not pass a request of the master (100) which has not been granted the access right from the right grant selection controller (603a).