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公开(公告)号：US20240097008A1
公开(公告)日：2024-03-21
申请号：US18462728
申请日：2023-09-07
Applicant: ROHM CO., LTD.
Inventor： Kazuhiro TAMURA , Naoki IZUMI , Hajime OKUDA
CPC classification number: H01L29/66681 , H01L29/086 , H01L29/0878 , H01L29/7824
Abstract: A semiconductor device includes: an n-type semiconductor layer; a p-type drift region formed in a surface layer of the n-type semiconductor layer; an n-type body region formed in the surface layer of the n-type semiconductor layer so as to be spaced apart from or adjacent to the p-type drift region; a p-type drain region formed in a surface layer of the p-type drift region; a p-type source region formed in a surface layer of the n-type body region; a gate insulating film formed over a surface of the n-type semiconductor layer so as to straddle the p-type drift region and the n-type body region; a gate electrode formed over the gate insulating film; and an n-type region formed in the surface layer of the p-type drift region and arranged between a side edge of the p-type drift region near the n-type body region and the p-type drain region.
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公开(公告)号：US20240308841A1
公开(公告)日：2024-09-19
申请号：US18601334
申请日：2024-03-11
Applicant: ROHM CO., LTD.
Inventor： Toma FUJITA , Martin Wilfried HELLER , Daisuke KAMINISHI , Naoki IZUMI
IPC: B81B3/00
CPC classification number: B81B3/0021 , B81B2201/0235 , B81B2203/0163 , B81B2203/0307 , B81B2203/04 , B81B2207/07
Abstract: The present disclosure provides a MEMS device including a device wafer, a cap wafer and a bonding layer. The device wafer includes: a device substrate, having a first main surface, a second main surface opposite to the first main surface, and a cavity recessed along a first direction from the first main surface toward the second main surface; a sensor unit, located within the cavity and mechanically connected to and electrically insulated from the device substrate by a single anchor; and a device wiring, electrically coupled to the sensor unit. The cap wafer includes: a cap substrate, facing the device wafer from a side of the first main surface; and a cap wiring, electrically coupled to the device wiring. The bonding layer bonds the device wafer with the cap wafer, and the device wiring is directly connected to the bonding layer.
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公开(公告)号：US20240290784A1
公开(公告)日：2024-08-29
申请号：US18437494
申请日：2024-02-09
Applicant: ROHM CO., LTD.
Inventor： Takeshi ISHIDA , Naoki IZUMI , Shoji TAKEI
IPC: H01L27/088 , H01L21/3215 , H01L21/8234 , H01L21/8236 , H01L29/49
CPC classification number: H01L27/0883 , H01L21/32155 , H01L21/823437 , H01L21/8236 , H01L29/4983
Abstract: An enhancement type MOSFET includes: a semiconductor layer having a first main surface on one side and a second main surface on another side, and having a p-type region in a surface layer region on the side of the first main surface; an n-type source region and an n-type drain region formed at an interval from each other in a surface layer region of the p-type region; a channel region formed between the n-type source region and the n-type drain region; a gate insulating film disposed on the channel region; and a polysilicon gate formed on the gate insulating film, wherein at least a main portion of the polysilicon gate is made of non-doped polysilicon.
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公开(公告)号：US20230352545A1
公开(公告)日：2023-11-02
申请号：US18350765
申请日：2023-07-12
Applicant: ROHM CO., LTD.
Inventor： Keiji WADA , Daisuke ICHIKAWA , Mitsuhide KORI , Naoki IZUMI , Bungo TANAKA
CPC classification number: H01L29/407 , H01L29/0626 , H01L29/7816
Abstract: A semiconductor device includes a chip that has a first main surface on one side and a second main surface on another side, a pn-junction portion that is formed in an interior of the chip such as to extend along the first main surface, a device region that is provided in the first main surface, a first trench structure that is formed in the first main surface such as to penetrate through the pn-junction portion and demarcates the device region in the first main surface, and a second trench structure that is formed in the first main surface such as to penetrate through the pn-junction portion and demarcates the device region in a region further to the device region side than the first trench structure.
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公开(公告)号：US20130270633A1
公开(公告)日：2013-10-17
申请号：US13914139
申请日：2013-06-10
Applicant: ROHM CO., LTD.
Inventor： Naoki IZUMI
IPC: H01L27/088
CPC classification number: H01L27/088 , H01L29/0696 , H01L29/4238 , H01L29/7813
Abstract: A semiconductor device according to the present invention includes: a body region of a first conductive type; trenches formed by digging in from a top surface of the body region; gate electrodes embedded in the trenches; source regions of a second conductive type formed at sides of the trenches in a top layer portion of the body region; and body contact regions of the first conductive type, penetrating through the source regions in a thickness direction and contacting the body region. The body contact regions are formed in a zigzag alignment in a plan view. With respect to a column formed by the body contact regions aligned in a predetermined column direction, the trenches are disposed at both sides in a row direction orthogonal to the column direction in a plan view, extend in the column direction, and form meandering lines each connecting a plurality of curved portions so that a predetermined gap in the row direction is formed respectively between adjacent trenches extending in the column direction and between the trenches and the body contact regions.
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Patent Agency Ranking
公开(公告)号：US20240400374A1
公开(公告)日：2024-12-05
申请号：US18676461
申请日：2024-05-28
Applicant: ROHM CO., LTD.
Inventor： Toma FUJITA , Martin Wilfried HELLER , Naoki IZUMI
IPC: B81B3/00 , B81C1/00 , G01P15/08 , G01P15/125
Abstract: The MEMS device includes a device wafer having a first principal surface and a second principal surface that is on the opposite side of to the first principal surface, a cap wafer facing the first principal surface of the device wafer, and a bonding layer bonding the device wafer and the cap wafer. The device wafer includes a device substrate having a cavity recessed in the Z direction from the first principal surface toward the second principal surface, a sensor unit that is positioned in the cavity and includes a fixed electrode and a movable electrode facing the fixed electrode, and a bump stopper that is disposed on a surface of the movable electrode, the surface being a surface on the side of the first principal surface, and that restricts displacement of the movable electrode in a direction moving closer to the cap wafer in the Z direction.
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公开(公告)号：US20240097028A1
公开(公告)日：2024-03-21
申请号：US18459699
申请日：2023-09-01
Applicant: ROHM CO., LTD.
Inventor： Kazuhiro TAMURA , Naoki IZUMI , Yusuke SHIMIZU
CPC classification number: H01L29/7824 , H01L29/086 , H01L29/0878 , H01L29/1095 , H01L29/66681
Abstract: A semiconductor device includes an n-type semiconductor layer, a p-type drift region formed in a surface layer portion of the semiconductor layer, an n-type body region formed in the surface layer portion of the semiconductor layer, a p-type drain region formed in a surface layer portion of the drift region, a p-type source region formed in a surface layer portion of the body region, a gate insulating film formed on a surface of the semiconductor layer, and a polysilicon gate formed on the gate insulating film, wherein a region extending from the source region to a side edge of the drift region is a channel region, and wherein the polysilicon gate includes a p-type first portion facing at least a portion of the channel region, and an n-type second portion facing at least a portion of the drift region.
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公开(公告)号：US20190393337A1
公开(公告)日：2019-12-26
申请号：US16563309
申请日：2019-09-06
Applicant: ROHM CO., LTD.
Inventor： Naoki IZUMI
IPC: H01L29/78 , H01L29/423 , H01L29/66
Abstract: A semiconductor device includes a semiconductor layer. A first conductivity type region is formed on a base layer portion of the semiconductor layer. A body region of a second conductivity type is formed on the semiconductor layer to be in contact with the first conductivity type region. A trench in which a gate electrode is embedded through a gate insulating film is formed on the semiconductor layer. The trench penetrates through the body region, so that a deepest portion thereof reaches the first conductivity type region. A source region of the first conductivity type is formed on a surface layer portion of the semiconductor layer around the trench. The gate insulating film includes a thick-film portion having a relatively large thickness on a bottom surface of the trench.
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公开(公告)号：US20160190311A1
公开(公告)日：2016-06-30
申请号：US15062696
申请日：2016-03-07
Applicant: ROHM CO., LTD.
Inventor： Naoki IZUMI , Tomoyasu SADA
CPC classification number: H01L29/7824 , H01L29/0878 , H01L29/1083 , H01L29/1095 , H01L29/402 , H01L29/42368 , H01L29/66681
Abstract: A semiconductor device according to the present invention includes: an insulating layer; a semiconductor layer of a first conductive type laminated on the insulating layer; an annular deep trench having a thickness reaching the insulating layer from a top surface of the semiconductor layer; a body region of a second conductive type formed across an entire thickness of the semiconductor layer along a side surface of the deep trench in an element forming region surrounded by the deep trench; a drift region of the first conductive type constituted of a remainder region besides the body region in the element forming region; a source region of the first conductive type formed in a top layer portion of the body region; a drain region of the first conductive type formed in a top layer portion of the drift region; and a first conductive type region formed in the drift region, having a deepest portion reaching a position deeper than the drain region, and having a first conductive type impurity concentration higher than the first conductive type impurity concentration of the semiconductor layer and lower than the first conductive type impurity concentration of the drain region.
Abstract translation: 根据本发明的半导体器件包括：绝缘层; 层叠在绝缘层上的第一导电类型的半导体层; 环形深沟槽，其厚度从半导体层的顶表面到达绝缘层; 在由所述深沟槽包围的元件形成区域中沿着所述深沟槽的侧表面横跨所述半导体层的整个厚度形成的第二导电类型的主体区域; 所述第一导电类型的漂移区域由除了所述元件形成区域中的所述主体区域之外的余下区域构成; 所述第一导电类型的源极区域形成在所述主体区域的顶层部分中; 所述第一导电类型的漏区形成在所述漂移区的顶层部分中; 以及形成在所述漂移区域中的第一导电类型区域，其最深部分到达比所述漏极区域更深的位置，并且具有比所述半导体层的所述第一导电类型杂质浓度高的第一导电型杂质浓度，并且低于所述第一导电类型区域 漏区的导电型杂质浓度。
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公开(公告)号：US20200235236A1
公开(公告)日：2020-07-23
申请号：US16796717
申请日：2020-02-20
Applicant: ROHM CO., LTD.
Inventor： Naoki IZUMI
IPC: H01L29/78 , H01L29/66 , H01L29/423
Abstract: A semiconductor device includes a semiconductor layer. A first conductivity type region is formed on a base layer portion of the semiconductor layer. A body region of a second conductivity type is formed on the semiconductor layer to be in contact with the first conductivity type region. A trench in which a gate electrode is embedded through a gate insulating film is formed on the semiconductor layer. The trench penetrates through the body region, so that a deepest portion thereof reaches the first conductivity type region. A source region of the first conductivity type is formed on a surface layer portion of the semiconductor layer around the trench. The gate insulating film includes a thick-film portion having a relatively large thickness on a bottom surface of the trench.
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