公开(公告)号：US20230374698A1

公开(公告)日：2023-11-23

申请号：US18361951

申请日：2023-07-31

Applicant: ROHM CO., LTD.

Inventor： Makoto TAKAMURA ,  Takuji MAEKAWA ,  Mitsuru MORIMOTO ,  Noriyuki MASAGO ,  Takayasu OKA

IPC: C30B25/12 ,  H01L21/02 ,  C30B25/10 ,  C30B25/20 ,  C30B29/36 ,  C30B25/14 ,  C23C16/32 ,  C23C16/458 ,  C23C16/46 ,  C23C16/455

CPC classification number: C30B25/12 ,  H01L21/02529 ,  H01L21/02378 ,  H01L21/02634 ,  C30B25/10 ,  C30B25/20 ,  C30B29/36 ,  C30B25/14 ,  C23C16/325 ,  C23C16/4587 ,  C23C16/46 ,  C23C16/45502

Abstract: A fabricating apparatus (2) of an sic epitaxial wafer disclosed herein includes: a growth furnace (100A); a gas mixing preliminary chamber (107) disposed outside the growth furnace and configured to mix carrier gas and/or material gas and to regulate a pressure thereof; a wafer boat (210) configured so that a plurality of SiC wafer pairs (200WP), in which two substrates each having an SiC single crystal in contact with each other in a back-to-back manner, are disposed at equal intervals with a gap therebetween; and a heating unit (101) configured to heat the wafer boat disposed in the growth furnace to an epitaxial growth temperature. The carrier gas and/or the material gas are introduced into the growth furnace after preliminarily being mixed and pressure-regulated in the gas mixing preliminary chamber (107) to grow an SiC layer on a surface of each of the plurality of SiC wafer pairs.

公开(公告)号：US20230369412A1

公开(公告)日：2023-11-16

申请号：US18357175

申请日：2023-07-24

Applicant: ROHM CO., LTD.

Inventor： Makoto TAKAMURA ,  Takuji MAEKAWA ,  Mitsuru MORIMOTO ,  Noriyuki MASAGO ,  Takayasu OKA

IPC: H01L29/16 ,  C30B29/36 ,  H01L29/04 ,  H01L21/02

CPC classification number: H01L29/1608 ,  H01L29/1606 ,  C30B29/36 ,  H01L29/04 ,  H01L21/02444 ,  H01L21/02447 ,  H01L21/02499 ,  H01L21/02529 ,  H01L21/02595 ,  H01L21/02694 ,  H01L29/872

Abstract: A semiconductor substrate (1) disclosed herein includes: an SiC single crystal substrate (10SB); a graphene layer (11GR) disposed on an Si plane of the SiC single crystal substrate (10SB); an SiC epitaxial growth layer (12RE) disposed above the SiC single crystal substrate (10SB) via the graphene layer (11GR); and a polycrystalline Si layer (15PS) disposed on an Si plane of the SiC epitaxial growth layer (12RE). The semiconductor substrate may include a graphite substrate or an silicon substrate disposed on a polycrystalline Si layer (15PS). The semiconductor substrate may further include an SiC polycrystalline growth layer (18PC) disposed on a C plane of the SiC epitaxial growth layer (12RE). Consequently, the present disclosure provides a low-cost and high-quality semiconductor substrate and a fabrication method thereof.

公开(公告)号：US20230369400A1

公开(公告)日：2023-11-16

申请号：US18356223

申请日：2023-07-21

Applicant: ROHM CO., LTD.

Inventor： Makoto TAKAMURA ,  Takuji MAEKAWA ,  Mitsuru MORIMOTO ,  Noriyuki MASAGO ,  Takayasu OKA

IPC: H01L29/06 ,  H01L29/04 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/872 ,  H01L29/16

CPC classification number: H01L29/0684 ,  H01L29/045 ,  H01L21/02447 ,  H01L29/7813 ,  H01L21/02513 ,  H01L21/02595 ,  H01L21/02378 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/6606 ,  H01L29/872 ,  H01L29/1608 ,  H01L21/02658 ,  H01L21/02529

Abstract: A semiconductor substrate (1) according to an embodiment includes: a hexagonal SiC single crystal layer (13I); an SiC epitaxial growth layer (12E) disposed on an Si plane of an SiC single crystal layer (13I); and an SiC polycrystalline growth layer (18PC) disposed on a C plane opposite to the Si plane of the SiC single crystal layer (13I). The SiC single crystal layer (13I) includes a single crystal SiC thin layer (10HE) obtained by weakening the hydrogen ion implantation layer (10HI), and a phosphorus ion implantation layer (10PI). The phosphorus ion implantation layer (10PI) is disposed between the single crystal SiC thin layer (10HE) and the SiC polycrystalline growth layer (18PC). Consequently, the present disclosure provides a low-cost and high-quality semiconductor substrate and a fabrication method thereof.

公开(公告)号：US20230317450A1

公开(公告)日：2023-10-05

申请号：US18330447

申请日：2023-06-07

Applicant: ROHM CO., LTD.

Inventor： Noriyuki MASAGO ,  Takuji MAEKAWA ,  Mitsuru MORIMOTO ,  Takayasu OKA

IPC: H01L21/02 ,  H01L29/16

CPC classification number: H01L21/02529 ,  H01L29/1608 ,  H01L21/02444 ,  H01L21/02378

Abstract: A semiconductor substrate (1) includes: an SiC single crystal substrate (10SB), a first graphene layer (11GR1) disposed on an Si plane of the SiC single crystal substrate 10SB; an SiC epitaxial growth layer (12RE) formed above the SiC single crystal substrate via the first graphene layer; and a second graphene layer (11GR2) disposed on an Si plane of the SiC epitaxial growth layer. There is also included an SiC polycrystalline substrate (16P) provisionally bonded onto the SiC epitaxial growth layer via the second graphene layer. The SiC single crystal substrate is able to be reused by being separated from the SiC epitaxial growth layer. This semiconductor substrate further includes an SiC polycrystalline growth layer (18PC) CVD grown on the C plane of the SiC epitaxial growth layer; and the SiC epitaxial growth layer is transferred to the SiC polycrystalline growth layer.