公开(公告)号：US20150089280A1

公开(公告)日：2015-03-26

申请号：US14038334

申请日：2013-09-26

申请人： Raanan Sade ,  Ron Gabor ,  Deep K. Buch ,  Theodros Yigzaw ,  Stanislav Shwartsman

发明人： Raanan Sade ,  Ron Gabor ,  Deep K. Buch ,  Theodros Yigzaw ,  Stanislav Shwartsman

IPC分类号： G06F11/07

CPC分类号： G06F11/073 ,  G06F11/0793 ,  G06F11/08

摘要： Mechanisms for handling multiple data errors that occur simultaneously are provided. A processing device may determine whether multiple data errors occur in memory locations that are within a range of memory locations. If the multiple memory locations are within the range of memory locations, the processing device may continue with a recovery process. If one of the multiple memory locations is outside of the range of memory locations, the processing device may halt the recovery process.

摘要翻译： 提供了同时处理多个数据错误的机制。 处理设备可以确定在存储器位置范围内的存储器位置中是否发生多个数据错误。 如果多个存储器位置在存储器位置的范围内，则处理设备可以继续恢复过程。 如果多个存储器位置中的一个位于存储器位置的范围之外，则处理设备可以停止恢复过程。

公开(公告)号：US20170177429A1

公开(公告)日：2017-06-22

申请号：US14977354

申请日：2015-12-21

申请人： Tomer Stark ,  Ron Gabor ,  Joseph Nuzman ,  Raanan Sade ,  Bryant E. Bigbee

发明人： Tomer Stark ,  Ron Gabor ,  Joseph Nuzman ,  Raanan Sade ,  Bryant E. Bigbee

IPC分类号： G06F11/07 ,  G06F3/06

CPC分类号： G06F11/0751 ,  G06F9/38 ,  G06F11/073 ,  G06F12/109 ,  G06F12/145 ,  G06F2212/1032 ,  G06F2212/1052 ,  G06F2212/656

摘要： Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.

公开(公告)号：US20160124802A1

公开(公告)日：2016-05-05

申请号：US14531498

申请日：2014-11-03

申请人： Ron Gabor ,  Raanan Sade ,  Joseph Nuzman

发明人： Ron Gabor ,  Raanan Sade ,  Joseph Nuzman

IPC分类号： G06F11/10 ,  H03M13/00 ,  H03M13/09

CPC分类号： G06F11/10

摘要： Systems and methods for memory corruption detection. An example processing system comprises a processing core including a register to store a base address of a memory corruption detection (MCD) table. The processing core is configured to validate a pointer referenced by a memory access instruction, by comparing a first value derived from a first portion of the pointer to a second value stored in the MCD table at an offset referenced by a second portion of the pointer.

摘要翻译： 内存损坏检测的系统和方法 示例性处理系统包括处理核心，其包括用于存储存储器破坏检测（MCD）表的基址的寄存器。 处理核心被配置为通过将由指针的第一部分导出的第一值与由指针的第二部分引用的偏移量相对应地存储在MCD表中的第二值进行比较来验证由存储器访问指令引用的指针。

公开(公告)号：US09003421B2

公开(公告)日：2015-04-07

申请号：US11288823

申请日：2005-11-28

申请人： Ron Gabor ,  Gad Sheaffer ,  Avi Mendelson ,  Uri C. Weiser ,  Hong Wang

发明人： Ron Gabor ,  Gad Sheaffer ,  Avi Mendelson ,  Uri C. Weiser ,  Hong Wang

IPC分类号： G06F9/46 ,  G06F9/30 ,  G06F9/48 ,  G06F9/50

CPC分类号： G06F9/4843 ,  G06F9/461 ,  G06F9/5027 ,  G06F2209/5018

摘要： Disclosed are embodiments of a system, methods and mechanism for using idle thread units to perform acceleration threads that are transparent to the operating system. When the operating system scheduler has no work to schedule on the idle thread units, the operating system may issue a halt or monitor/mwait or other instruction to place the thread unit into an idle state. While the thread unit is idle, from the operating system perspective, the thread unit may be utilized to perform speculative acceleration threads in order to accelerate threads running on non-idle thread units. The context of the idle thread unit is saved prior to execution of the acceleration thread and is restored when the operating system requires use of the thread unit. The acceleration threads are transparent to the operating system. Other embodiments are also described and claimed.

摘要翻译： 公开了使用空闲螺纹单元执行对操作系统透明的加速度线程的系统，方法和机构的实施例。 当操作系统调度器没有在空闲线程单元上进行调度时，操作系统可以发出停止或监视/等待或其他指令来将线程单元置于空闲状态。 当线程单元处于空闲状态时，从操作系统的角度来看，线程单元可用于执行推测加速线程，以加速在非空闲线程单元上运行的线程。 空闲线程单元的上下文在执行加速线程之前被保存，并且当操作系统需要使用线程单元时被恢复。 加速线程对操作系统是透明的。 还描述和要求保护其他实施例。

公开(公告)号：US20140006817A1

公开(公告)日：2014-01-02

申请号：US13534601

申请日：2012-06-27

申请人： Nadav Bonen ,  Ron Gabor ,  Zeev Sperber ,  Vjekoslav Svilan ,  David N. Mackintosh ,  Jose A. Baiocchi Paredes ,  Naveen Kumar ,  Shantanu Gupta

发明人： Nadav Bonen ,  Ron Gabor ,  Zeev Sperber ,  Vjekoslav Svilan ,  David N. Mackintosh ,  Jose A. Baiocchi Paredes ,  Naveen Kumar ,  Shantanu Gupta

IPC分类号： G06F1/32

CPC分类号： G06F1/3243 ,  G06F1/3287 ,  G06F9/30083 ,  G06F9/3869 ,  G06F9/3885 ,  Y02B70/123 ,  Y02B70/126 ,  Y02D10/152 ,  Y02D10/171

摘要： In an embodiment, the present invention includes an execution unit to execute instructions of a first type, a local power gate circuit coupled to the execution unit to power gate the execution unit while a second execution unit is to execute instructions of a second type, and a controller coupled to the local power gate circuit to cause it to power gate the execution unit when an instruction stream does not include the first type of instructions. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括执行单元，用于执行第一类型的指令，耦合到执行单元的本地电源门电路，以在第二执行单元执行第二类型的指令时对所述执行单元进行电源门控，以及 控制器，其耦合到所述本地电源门电路，以使得当指令流不包括所述第一类型的指令时，所述控制器对所述执行单元进行供电。 描述和要求保护其他实施例。

公开(公告)号：US08543796B2

公开(公告)日：2013-09-24

申请号：US12290962

申请日：2008-11-05

申请人： Ohad Falik ,  Lihu Rappoport ,  Ron Gabor ,  Yulia Kurolap ,  Michael Mishaeli

发明人： Ohad Falik ,  Lihu Rappoport ,  Ron Gabor ,  Yulia Kurolap ,  Michael Mishaeli

IPC分类号： G06F9/30

CPC分类号： G06F9/30145 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/3017 ,  G06F9/30181 ,  G06F9/325 ,  G06F9/3855 ,  G06F9/3857

摘要： In one embodiment, the present invention includes an instruction decoder that can receive an incoming instruction and a path select signal and decode the incoming instruction into a first instruction code or a second instruction code responsive to the path select signal. The two different instruction codes, both representing the same incoming instruction may be used by an execution unit to perform an operation optimized for different data lengths. Other embodiments are described and claimed.

公开(公告)号：US07725745B2

公开(公告)日：2010-05-25

申请号：US11642128

申请日：2006-12-19

申请人： Ron Gabor ,  Hong Jiang ,  Alon Naveh ,  Doron Rajwan ,  James Varga ,  Gady Yearim ,  Yuval Yosef

发明人： Ron Gabor ,  Hong Jiang ,  Alon Naveh ,  Doron Rajwan ,  James Varga ,  Gady Yearim ,  Yuval Yosef

IPC分类号： G06F1/32 ,  G06F1/00 ,  G06F9/40

CPC分类号： G06F1/3203

摘要： Forming a plurality of pipeline orderings, each pipeline ordering comprising one of a sequential, a parallel, or a sequential and parallel combination of a plurality of stages of a pipeline, analyzing the plurality of pipeline orderings to determine a total power of each of the orderings, and selecting one of the plurality of pipeline orderings based on the determined total power of each of the plurality of pipeline orderings.

公开(公告)号：US07650273B2

公开(公告)日：2010-01-19

申请号：US11231619

申请日：2005-09-21

申请人： Ron Gabor ,  Nathaniel Leibowitz ,  Meir Tsadik ,  Yoram Kulbak

发明人： Ron Gabor ,  Nathaniel Leibowitz ,  Meir Tsadik ,  Yoram Kulbak

IPC分类号： G06F9/44

CPC分类号： G06F11/3457 ,  G06F17/5022

摘要： An embodiment of the present invention is a technique to simulate performance of a multi-core system. A micro-architecture effect is estimated from each core in the multi-core system. A model of a memory hierarchy associated with each core is simulated. The simulated model of the memory hierarchy is superpositioned on the estimated micro-architecture effect to produce a performance figure for the multi-core system.

摘要翻译： 本发明的一个实施例是一种模拟多核系统性能的技术。 从多核系统中的每个核心估计微架构效应。 模拟与每个核心相关联的内存层次的模型。 存储器层次的模拟模型叠加在估计的微架构效应上，以产生多核系统的性能指标。

公开(公告)号：US20080148076A1

公开(公告)日：2008-06-19

申请号：US11642128

申请日：2006-12-19

申请人： Ron Gabor ,  Hong Jiang ,  Alon Naveh ,  Doron Rajwan ,  James Varga ,  Gady Yearim ,  Yuval Yosef

发明人： Ron Gabor ,  Hong Jiang ,  Alon Naveh ,  Doron Rajwan ,  James Varga ,  Gady Yearim ,  Yuval Yosef

IPC分类号： G06F1/28

CPC分类号： G06F1/3203

摘要： Forming a plurality of pipeline orderings, each pipeline ordering comprising one of a sequential, a parallel, or a sequential and parallel combination of a plurality of stages of a pipeline, analyzing the plurality of pipeline orderings to determine a total power of each of the orderings, and selecting one of the plurality of pipeline orderings based on the determined total power of each of the plurality of pipeline orderings.

摘要翻译： 形成多个流水线排序，每个流水线排序包括流水线的多个阶段的顺序，并行或顺序和并行组合中的一个，分析多个流水线排序以确定每个排序的总功率 并且基于所确定的多个流水线排序中的每一个的总功率来选择多个流水线排序中的一个。

公开(公告)号：US09672019B2

公开(公告)日：2017-06-06

申请号：US12978557

申请日：2010-12-25

申请人： David J. Sager ,  Ruchira Sasanka ,  Ron Gabor ,  Shlomo Raikin ,  Joseph Nuzman ,  Leeor Peled ,  Jason A. Domer ,  Ho-Seop Kim ,  Youfeng Wu ,  Koichi Yamada ,  Tin-Fook Ngai ,  Howard H. Chen ,  Jayaram Bobba ,  Jeffery J. Cook ,  Omar M. Shaikh ,  Suresh Srinivas

发明人： David J. Sager ,  Ruchira Sasanka ,  Ron Gabor ,  Shlomo Raikin ,  Joseph Nuzman ,  Leeor Peled ,  Jason A. Domer ,  Ho-Seop Kim ,  Youfeng Wu ,  Koichi Yamada ,  Tin-Fook Ngai ,  Howard H. Chen ,  Jayaram Bobba ,  Jeffery J. Cook ,  Omar M. Shaikh ,  Suresh Srinivas

IPC分类号： G06F9/45 ,  G06F9/38 ,  G06F9/54 ,  G06F11/36

CPC分类号： G06F8/4442 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/54 ,  G06F11/3612 ,  G06F11/3636 ,  G06F11/3648 ,  G06F2213/0038

摘要： Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.